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參數(shù)資料
| 型號(hào)： | MT46V128M4FN-75E:C |
| 元件分類： | DRAM |
| 英文描述： | 128M X 4 DDR DRAM, 0.75 ns, PBGA60 |
| 封裝： | 10 X 12.50 MM, FBGA-60 |
| 文件頁數(shù)： | 30/94頁 |
| 文件大?。?/td> | 4179K |
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09005aef80a1d9e7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_2.fm - Rev. J 1/06 EN
36
2000–2005 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR SDRAM
Operations
Figure 20:
WRITE Command
Note:
CA = Column address; BA = Bank address; EN AP = Enable auto precharge; and DIS AP =
Disable auto precharge.
Data for any WRITE burst may be followed by a subsequent READ command. To follow a
Data for any WRITE burst may be truncated by a subsequent READ command, as shown
Note that only the data-in pairs that are registered prior to the tWTR period are written
to the internal array, and any subsequent data-in should be masked with DM, as shown
Data for any WRITE burst may be followed by a subsequent PRECHARGE command. To
follow a WRITE without truncating the WRITE burst, tWR should be met, as shown in
Data for any WRITE burst may be truncated by a subsequent PRECHARGE command, as
shown in Figure 29 on page 45 and Figure 30 on page 46. Only the data-in pairs regis-
tered prior to the tWR period are written to the internal array; any subsequent data-in
mand, a subsequent command to the same bank cannot be issued until tRP is met.
CS#
WE#
CAS#
RAS#
CKE
CA
A10
BA0,1
HIGH
EN AP
DIS AP
BA
CK
CK#
DON’T CARE
x8: A12
x16: A11, A12
x4: A0–A9, A11, A12
x8: A0–A9, A11
x16: A0–A9
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| MT46V128M4P-75L:C | 128M X 4 DDR DRAM, 0.75 ns, PDSO66 |
| MT46V128M4P-75ZLIT:C | 128M X 4 DDR DRAM, 0.75 ns, PDSO66 |
| MT46V64M4TG-75E | 64M X 4 DDR DRAM, 0.75 ns, PDSO66 |
| MT46V64M4FG-75Z | 64M X 4 DDR DRAM, 0.75 ns, PBGA60 |
| MT47H128M8HQ-3AT | 128M X 8 DDR DRAM, 0.4 ns, PBGA60 |
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