參數(shù)資料
型號(hào)： MT46V128M4FN-75E:C
元件分類： DRAM
英文描述： 128M X 4 DDR DRAM, 0.75 ns, PBGA60
封裝： 10 X 12.50 MM, FBGA-60
文件頁(yè)數(shù)： 29/94頁(yè)
文件大?。?/td> 4179K
09005aef80a1d9e7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_2.fm - Rev. J 1/06 EN
35
2000–2005 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR SDRAM
Operations
WRITEs
WRITE bursts are initiated with a WRITE command, as shown in Figure 20 on page 36.
The starting column and bank addresses are provided with the WRITE command, and
auto precharge is either enabled or disabled for that access. If auto precharge is enabled,
the row being accessed is precharged at the completion of the burst and after the tWR
time.
Note:
For the WRITE commands used in the following illustrations, auto precharge is dis-
abled.
During WRITE bursts, the first valid data-in element will be registered on the first rising
edge of DQS following the WRITE command, and subsequent data elements will be reg-
istered on successive edges of DQS. The LOW state on DQS between the WRITE com-
mand and the first rising edge is known as the write preamble; the LOW state on DQS
following the last data-in element is known as the write postamble.
The time between the WRITE command and the first corresponding rising edge of
DQS (tDQSS) is specified with a relatively wide range (from 75 percent to 125 per-
cent of one clock cycle). All of the WRITE diagrams show the nominal case, and
where the two extreme cases (i.e., tDQSS [MIN] and tDQSS [MAX]) might not be intui-
tive, they have also been included. Figure 21 on page 37 shows the nominal case and
the extremes of tDQSS for BL = 4. Upon completion of a burst, assuming no other
commands have been initiated, the DQ will remain High-Z and any additional input
data will be ignored.
Data for any WRITE burst may be concatenated with or truncated with a subsequent
WRITE command. In either case, a continuous flow of input data can be maintained.
The new WRITE command can be issued on any positive edge of clock following the pre-
vious WRITE command. The first data element from the new burst is applied after either
the last element of a completed burst or the last desired data element of a longer burst
which is being truncated. The new WRITE command should be issued x cycles after the
first WRITE command, where x equals the number of desired data element pairs (pairs
are required by the 2n-prefetch architecture).
Figure 22 on page 38 shows concatenated bursts of 4. An example of nonconsecutive
WRITEs is shown in Figure 23 on page 39. Full-speed random write accesses within a
page or pages can be performed as shown in Figure 24 on page 40.
相關(guān)PDF資料
PDF描述
MT46V128M4P-75L:C 128M X 4 DDR DRAM, 0.75 ns, PDSO66
MT46V128M4P-75ZLIT:C 128M X 4 DDR DRAM, 0.75 ns, PDSO66
MT46V64M4TG-75E 64M X 4 DDR DRAM, 0.75 ns, PDSO66
MT46V64M4FG-75Z 64M X 4 DDR DRAM, 0.75 ns, PBGA60
MT47H128M8HQ-3AT 128M X 8 DDR DRAM, 0.4 ns, PBGA60
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