參數(shù)資料
型號(hào)： MT46V128M4FN-75E:C
元件分類： DRAM
英文描述： 128M X 4 DDR DRAM, 0.75 ns, PBGA60
封裝： 10 X 12.50 MM, FBGA-60
文件頁(yè)數(shù)： 24/94頁(yè)
文件大?。?/td> 4179K
09005aef80a1d9e7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_2.fm - Rev. J 1/06 EN
30
2000–2005 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR SDRAM
Operations
Figure 15:
Nonconsecutive READ Bursts
Notes: 1. DO n (or b) = data-out from column n (or column b).
2. BL = 4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first).
3. Three subsequent elements of data-out appear in the programmed order following DO n.
4. Three (or seven) subsequent elements of data-out appear in the programmed order fol-
lowing DO b.
5. Shown with nominal tAC, tDQSCK, and tDQSQ.
CK
CK#
COMMAND
READ
NOP
ADDRESS
Bank,
Col n
READ
Bank,
Col b
COMMAND
ADDRESS
CL = 2
CK
CK#
COMMAND
ADDRESS
DQ
DQS
CL = 2.5
DQ
DQS
DO
n
T0
T1
T2
T3
T2n
T3n
T4
T5
T5n
T6
READ
NOP
Bank,
Col n
READ
Bank,
Col b
T0
T1
T2
T3
T2n
T3n
T4
T5
T5n
T6
DO
b
DO
n
DO
b
DON’T CARE
TRANSITIONING DATA
COMMAND
ADDRESS
CK
CK#
COMMAND
ADDRESS
DQ
DQS
CL = 3
READ
NOP
Bank,
Col n
READ
Bank,
Col b
T0
T1
T2
T3
T3n
T4
T5
T6
DO
n
DO
b
T4n
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