參數(shù)資料
型號(hào)： MT46V128M4FN-75E:C
元件分類(lèi)： DRAM
英文描述： 128M X 4 DDR DRAM, 0.75 ns, PBGA60
封裝： 10 X 12.50 MM, FBGA-60
文件頁(yè)數(shù)： 20/94頁(yè)
文件大?。?/td> 4179K
09005aef80a1d9e7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_2.fm - Rev. J 1/06 EN
27
2000–2005 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR SDRAM
Operations
Data from any READ burst may be truncated with a BURST TERMINATE command, as
shown in Figure 17 on page 32. The BURST TERMINATE latency is equal to the read
(CAS) latency, i.e., the BURST TERMINATE command should be issued x cycles after the
READ command, where x equals the number of desired data element pairs (pairs are
required by the 2n-prefetch architecture).
Data from any READ burst must be completed or truncated before a subsequent WRITE
command can be issued. If truncation is necessary, the BURST TERMINATE command
must be used, as shown in Figure 18 on page 33. The tDQSS (NOM) case is shown; the
tDQSS (MAX) case has a longer bus idle time. (tDQSS [MIN] and tDQSS [MAX] are
defined in the section on WRITEs.)
A READ burst may be followed by, or truncated with, a PRECHARGE command to the
same bank provided that auto precharge was not activated.
The PRECHARGE command should be issued x cycles after the READ command, where
x equals the number of desired data element pairs (pairs are required by the 2n-prefetch
architecture). This is shown in Figure 19 on page 34. Following the PRECHARGE com-
mand, a subsequent command to the same bank cannot be issued until both tRAS and
tRP has been met. Part of the row precharge time is hidden during the access of the last
data elements.
Figure 12:
READ Command
Note:
CA = Column address; BA = Bank address; EN AP = Enable auto precharge; and DIS AP =
Disable auto precharge
CS#
WE#
CAS#
RAS#
CKE
CA
x4: A0–A9, A11, A12
x8: A0–A9, A11
x16: A0–A9
A10
BA0,1
HIGH
EN AP
DIS AP
BA
x8: A12
x16: A11, A12
CK
CK#
DON’T CARE
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