參數(shù)資料
型號(hào)： MT46V128M4FN-75E:C
元件分類： DRAM
英文描述： 128M X 4 DDR DRAM, 0.75 ns, PBGA60
封裝： 10 X 12.50 MM, FBGA-60
文件頁(yè)數(shù)： 2/94頁(yè)
文件大?。?/td> 4179K
09005aef80a1d9e7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_2.fm - Rev. J 1/06 EN
10
2000–2005 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR SDRAM
Ball/Pin Assignments and Descriptions
Table 2:
Ball/Pin Descriptions
FBGA
Numbers
TSOP
Numbers
Symbol
Type
Description
G2, G3
45, 46
CK, CK#
Input
Clock: CK and CK# are differential clock inputs. All address and control
input signals are sampled on the crossing of the positive edge of CK and
negative edge of CK#. Output data (DQ and DQS) is referenced to the
crossings of CK and CK#.
H3
44
CKE
Input
Clock enable: CKE HIGH activates and CKE LOW deactivates the internal
clock, input buffers and output drivers. Taking CKE LOW provides
PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks idle),
or ACTIVE POWER-DOWN (row ACTIVE in any bank). CKE is synchronous
for POWER-DOWN entry and exit, and for SELF REFRESH entry. CKE is
asynchronous for SELF REFRESH exit and for disabling the outputs. CKE
must be maintained HIGH throughout read and write accesses. Input
buffers (excluding CK, CK# and CKE) are disabled during POWER-DOWN.
Input buffers (excluding CKE) are disabled during SELF REFRESH. CKE is an
SSTL_2 input but will detect an LVCMOS
LOW level after VDD is applied
and until CKE is first brought HIGH, after which it becomes a SSTL_2
input only.
H8
24
CS#
Input
Chip select: CS# enables (registered LOW) and disables (registered HIGH)
the command decoder. All commands are masked when CS# is registered
HIGH. CS# provides for external bank selection on systems with multiple
banks. CS# is considered part of the command code.
H7, G8,
G7
23, 22,
21
RAS#, CAS#,
WE#
Input
Command inputs: RAS#, CAS#, and WE# (along with CS#) define the
command being entered.
3F
47
DM
Input
Input data mask: DM is an input mask signal for write data. Input data is
masked when DM is sampled HIGH along with that input data during a
WRITE access. DM is sampled on both edges of DQS. Although DM pins
are input-only, the DM loading is designed to match that of DQ and DQS
pins. For the x16, LDM is DM for DQ0–DQ7 and UDM is DM for DQ8–
DQ15. Pin 20 is a NC on x4 and x8.
F7, 3F
20, 47
LDM, UDM
J8, J7
26, 27
BA0, BA1
Input
Bank address inputs: BA0 and BA1 define to which bank an ACTIVE, READ,
WRITE, or PRECHARGE command is being applied.
K7, L8, L7,
M8, M2, L3,
L2, K3, K2,
J3, K8,
J2,H2
29, 30, 31,
32, 35, 36,
37, 38, 39,
40, 28
41, 42
A0, A1, A2,
A3, A4, A5,
A6, A7, A8,
A9, A10,
A11, A12
Input
Address inputs: Provide the row address for ACTIVE commands, and the
column address and auto precharge bit (A10) for READ/WRITE commands,
to select one location out of the memory array in the respective bank. A10
sampled during a PRECHARGE command determines whether the
PRECHARGE applies to one bank (A10 LOW, bank selected by BA0, BA1) or
all banks (A10 HIGH). The address inputs also provide the op-code during
a MODE REGISTER SET command. BA0 and BA1 define which mode
register (mode register or extended mode register) is loaded during the
LOAD MODE REGISTER (LMR) command.
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