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Table 2: Configuration Addressing – 2Gb
Architecture
128 Meg x 16
64 Meg x 32
Reduced Page-Size
Option 128 Meg x 16
Reduced Page-Size
Option 64 Meg x 32
Configuration
32 Meg x 16 x 4 banks 16 Meg x 32 x 4 banks
32 Meg x 16 x 4 banks
16 Meg x 32 x 4 banks
Refresh count
8K
Row addressing
16K A[13:0]
32K A[14:0]
Column addressing
2K A11, A[9:0]
1K A[9:0]
512 A[8:0]
respective architecture.
Figure 1: 2Gb Mobile LPDDR Part Numbering
MT 46 H 64M32 LF CK -6
IT :A
Micron Technology
Product Family
46 = Mobile LPDDR
Operating Voltage
H = 1.8/1.8V
Configuration
128 Meg x 16
64 Meg x 32
128 Meg x 32
256 Meg x 32
Addressing
LF = JEDEC-standard addressing
L2 = 2-die stack standard addressing
L4 = 4-die stack standard addressing
LG = Reduced page-size
R4 = 4-die stack reduced page-size addressing
Design Revision
:A = First generation
Operating Temperature
Blank = Commercial (0°C to +70°C)
IT = Industrial (–40°C to +85°C)
AT = Automotive (–40°C to +105°C)
Power
Blank = Standard IDD2/IDD6
Cycle Time (CL = 3)
-5 = 5ns tCK
-54 = 5.4ns tCK
-6 = 6ns tCK
-75 = 7.5ns tCK
Package Codes
CK = 60-ball (10mm x 11.5mm) VFBGA, “green”
CM = 90-ball (10mm x 13mm) VFBGA, “green”
JV = 168-ball (12mm x 12mm) VFBGA, “green”
KQ = 168-ball (12mm x 12mm) WFBGA, “green”
MA = 168-ball (12mm x 12mm) WFBGA, “green”
MC = 240-ball (14mm x 14mm) WFBGA, “green”
FBGA Part Marking Decoder
Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the
2Gb: x16, x32 Mobile LPDDR SDRAM
Features
PDF: 09005aef83a73286
2gb_ddr_mobile_sdram_t69m.pdf - Rev. M 11/10 EN
2
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