參數(shù)資料
型號(hào)： MT46H128M32L2JV-54AT:A
元件分類(lèi)： DRAM
英文描述： 128M X 32 DDR DRAM, 5 ns, PBGA168
封裝： 12 X 12 MM, GREEN, PLASTIC, VFBGA-168
文件頁(yè)數(shù)： 52/106頁(yè)
文件大?。?/td> 3431K
List of Figures
Figure 1: 2Gb Mobile LPDDR Part Numbering .................................................................................................. 2
Figure 2: Functional Block Diagram (x16) ......................................................................................................... 9
Figure 3: Functional Block Diagram (x32) ....................................................................................................... 10
Figure 4: 60-Ball VFBGA – Top View, x16 only ................................................................................................. 11
Figure 5: 90-Ball VFBGA – Top View, x32 only ................................................................................................. 12
Figure 6: 168-Ball FBGA – 12mm x 12mm (Top View), x32 only ........................................................................ 13
Figure 7: 240-Ball FBGA – 14mm x 14mm (Top View), x32 only ........................................................................ 14
Figure 8: Single Rank, Single Channel (1 Die) Package Block Diagram ............................................................. 17
Figure 9: Dual Rank, Single Channel (2 Die) Package Block Diagram ............................................................... 18
Figure 10: Dual Rank, Single Channel (4 Die) Package Block Diagram ............................................................. 19
Figure 11: 60-Ball VFBGA (10mm x 11.5mm), Package Code: CK ...................................................................... 20
Figure 12: 90-Ball VFBGA (10mm x 13mm), Package Code: CM ....................................................................... 21
Figure 13: 168-Ball VFBGA (12mm x 12mm), Package Code: JV ........................................................................ 22
Figure 14: 168-Ball WFBGA (12mm x 12mm), Package Code: KQ ..................................................................... 23
Figure 15: 168-Ball WFBGA (12mm x 12mm), Package Code: MA ..................................................................... 24
Figure 16: 240-Ball WFBGA (14mm x 14mm), Package Code: MC ..................................................................... 25
Figure 17: Typical Self Refresh Current vs. Temperature ................................................................................. 34
Figure 18: ACTIVE Command ........................................................................................................................ 46
Figure 19: READ Command ........................................................................................................................... 47
Figure 20: WRITE Command ......................................................................................................................... 48
Figure 21: PRECHARGE Command ................................................................................................................ 49
Figure 22: DEEP POWER-DOWN Command .................................................................................................. 50
Figure 23: Simplified State Diagram ............................................................................................................... 56
Figure 24: Initialize and Load Mode Registers ................................................................................................. 58
Figure 25: Alternate Initialization with CKE LOW ............................................................................................ 59
Figure 26: Standard Mode Register Definition ................................................................................................ 60
Figure 27: CAS Latency .................................................................................................................................. 63
Figure 28: Extended Mode Register ................................................................................................................ 64
Figure 29: Status Read Register Timing .......................................................................................................... 66
Figure 30: Status Register Definition .............................................................................................................. 67
Figure 31: READ Burst ................................................................................................................................... 70
Figure 32: Consecutive READ Bursts .............................................................................................................. 71
Figure 33: Nonconsecutive READ Bursts ........................................................................................................ 72
Figure 34: Random Read Accesses ................................................................................................................. 73
Figure 35: Terminating a READ Burst ............................................................................................................. 74
Figure 36: READ-to-WRITE ............................................................................................................................ 75
Figure 37: READ-to-PRECHARGE .................................................................................................................. 76
Figure 38: Data Output Timing – tDQSQ, tQH, and Data Valid Window (x16) ................................................... 77
Figure 39: Data Output Timing – tDQSQ, tQH, and Data Valid Window (x32) ................................................... 78
Figure 40: Data Output Timing – tAC and tDQSCK .......................................................................................... 79
Figure 41: Data Input Timing ......................................................................................................................... 81
Figure 42: Write – DM Operation ................................................................................................................... 82
Figure 43: WRITE Burst ................................................................................................................................. 83
Figure 44: Consecutive WRITE-to-WRITE ....................................................................................................... 84
Figure 45: Nonconsecutive WRITE-to-WRITE ................................................................................................. 84
Figure 46: Random WRITE Cycles .................................................................................................................. 85
Figure 47: WRITE-to-READ – Uninterrupting ................................................................................................. 86
Figure 48: WRITE-to-READ – Interrupting ...................................................................................................... 87
Figure 49: WRITE-to-READ – Odd Number of Data, Interrupting .................................................................... 88
Figure 50: WRITE-to-PRECHARGE – Uninterrupting ...................................................................................... 89
2Gb: x16, x32 Mobile LPDDR SDRAM
Features
PDF: 09005aef83a73286
2gb_ddr_mobile_sdram_t69m.pdf - Rev. M 11/10 EN
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2009 Micron Technology, Inc. All rights reserved.
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