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參數(shù)資料
| 型號(hào)： | MSM8129W-35 |
| 元件分類： | SRAM |
| 英文描述： | 128K X 8 STANDARD SRAM, 35 ns, CQCC32 |
| 封裝： | CERAMIC, LCC-32 |
| 文件頁(yè)數(shù)： | 5/9頁(yè) |
| 文件大?。?/td> | 74K |
| 代理商： | MSM8129W-35 |
MSM8129 - 020/025/35
ISSUE 2.0 April 2001
5
Notes:
(1) During the Read Cycle, WE is high.
(2) Address valid prior to or coincident with CS transition Low.
(3)
t
CHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced
to output voltage levels. These parameters are sampled and not 100% tested.
Read Cycle Timing Waveform (1,2)
Write Cycle No.1 Timing Waveform
t
RC
AA
OE
OH
Address
OE
CS
t OHZ(3)
t OLZ
t
ACS
t CLZ
t CHZ(3)
Data Valid
D0~7
High-Z
t AS(3)
t AW
t CW(4)
tWC
Address
OE
CS
t
WP(1)
t
OHZ(3,9)
WE
D0~7 out
t
DW
DH
D0~7 in
(6)
t
WR (2)
t
OW
High-Z
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