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參數(shù)資料
| 型號： | MSM8129W-35 |
| 元件分類： | SRAM |
| 英文描述： | 128K X 8 STANDARD SRAM, 35 ns, CQCC32 |
| 封裝： | CERAMIC, LCC-32 |
| 文件頁數(shù)： | 3/9頁 |
| 文件大?。?/td> | 74K |
| 代理商： | MSM8129W-35 |
MSM8129 - 020/025/35
ISSUE 2.0 April 2001
3
AC OPERATING CONDITIONS
Read Cycle
20
25
35
Parameter
Symbol
min
max
min
max
min
max
Units
Read Cycle Time
t
RC
20
-
25
-
35
-
ns
Address Access Time
t
AA
-20
-
25
-35
ns
Chip Select Access Time
t
ACS
-20
-
25
-35
ns
Output Enable to Output Valid
t
OE
-10
-
12
-15
ns
Output Hold from Address Change
t
OH
3
-
3-
ns
Chip Selection to Output in Low Z
t
CLZ
3
-
3-
ns
Output Enable to Output in Low Z
t
OLZ
0
-
0-
ns
Chip Deselection to Output in High Z(3) t
CHZ
-10
0
12
0
15
ns
Output Disable to Output in High Z(3)
t
OHZ
010
0
12
015
ns
Write Cycle
20
25
35
Parameter
Symbol
min
max
min
max
min
max
Unit
Write Cycle Time
t
WC
20
-
25
-
35
-
ns
Chip Selection to End of Write
t
CW
15
-
15
-
20
-
ns
Address Valid to End of Write
t
AW
15
-
15
-
20
-
ns
Address Setup Time
t
AS
0
-
0-
ns
Write Pulse Width
t
WP
15
-
15
-
20
-
ns
Write Recovery Time
t
WR
0
-
0-
ns
Write to Output in High Z
t
WHZ
010
0
12
015
ns
Data to Write Time Overlap
t
DW
10
-
12
-
15
-
ns
Data Hold from Write Time
t
DH
0
-
0-
ns
Output Active from End of Write
t
OW
6
-
6-
ns
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