參數(shù)資料
型號: MSC7112VM800
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號處理
英文描述: 32-BIT, 200 MHz, OTHER DSP, PBGA400
封裝: 17 X 17 MM, LEAD FREE, BGA-400
文件頁數(shù): 44/56頁
文件大?。?/td> 1489K
代理商: MSC7112VM800
Ha
rdwa
re
De
s
ign
Con
s
ide
ra
tion
s
M
SC7
1
2
Low-Cos
t1
6
-bit
DSP
with
DDR
Control
le
rDa
ta
She
e
t,
Re
v
.1
1
Fr
ees
ca
le
Sem
ic
ond
uc
tor
49
3.4.2
R
ese
tConfi
gur
a
tion
Pi
ns
Ta
h
o
w
sthe
MS
C
7
1
12
r
es
et
co
nfig
uration
s
ig
n
als
.Thes
es
ig
n
als
are
s
ampled
at
the
d
eas
se
rtion
(ris
ing
ed
ge)
of
PORESET
.Fo
rd
etai
ls,
r
ef
er
to
th
eR
eset
ch
ap
ter
o
fth
e
MSC
7
11
xRefer
ence
Man
u
al
.
3.
4.
3
B
oot
Af
te
ra
p
o
wer
-on
re
set
,the
PLL
is
by
pas
sed
an
d
th
e
dev
ic
e
is
di
rec
tly
cl
ocke
d
fr
o
m
th
e
CL
KIN
p
in.
Usi
ng
thi
sin
put
cl
oc
k,
the
s
yst
em
i
ni
tia
liz
es
us
ing
t
he
boot
loa
der
p
rog
ram
th
at
re
si
des
i
n
the
i
nt
e
rn
al
ROM.
Af
te
r
ini
tia
liz
a
tion
,t
he
DSP
c
or
e
ca
n
en
abl
e
t
he
PL
L
and
st
art
t
he
d
e
vi
ce
o
per
at
ing
at
a
hi
ghe
rs
pee
d.
The
M
S
C71
1
2
ca
n
boo
tf
rom
a
n
exte
rna
lhos
tth
rou
gh
the
HDI
16
or
downl
oa
d
a
u
ser
p
rog
ram
th
roug
h
the
I
2
C
por
t.
The
boo
tope
rat
ing
m
o
de
is
se
t
by
con
figur
ing
the
BM
[1–0
]si
gna
ls
sa
m
p
le
d
at
th
er
is
ing
edge
of
PO
RESE
T
,a
ss
hown
i
n
Ta
3.4.3.
1
HDI16
Boot
If
the
MSC
7
1
2
dev
ice
bo
ots
from
an
ex
ternal
h
o
st
th
ro
u
g
h
th
eHDI
1
6
,th
e
p
o
rt
is
co
n
fig
u
red
a
sf
o
llo
ws
:
O
p
er
ate
in
No
n
-DMA
mo
d
e.
Op
er
ate
in
p
o
lled
m
o
d
eo
n
th
ed
ev
ice
sid
e.
Op
er
ate
in
p
o
lled
m
o
d
eo
n
th
ee
x
ter
n
al
h
o
st
s
id
e.
E
x
ter
n
al
h
o
st
m
u
st
wr
ite
f
o
u
r1
6
-b
it
v
alu
es
at
a
t
im
e
with
th
ef
ir
st
wo
rd
as
th
em
o
st
s
ig
n
if
ican
tan
d
th
ef
o
u
rth
wo
rd
as
the
l
eas
t
si
gnifican
t.
Wh
en
b
o
tin
g
f
ro
m
a
p
o
wer
-o
n
r
es
et,
th
eHDI
1
6
is
ad
d
itio
n
ally
c
o
n
fig
u
rab
le
as
fo
llo
ws:
8
-or
16
-bit
mo
de
as
s
p
ecified
b
y
the
H8
BIT
pi
n.
D
ata
s
trob
eas
sp
eci
fi
ed
by
the
HDSP
an
d
HDDS
pi
n
s.
Th
es
e
pins
are
s
ampled
on
ly
on
the
d
eas
se
rtion
of
power
-o
n
res
et.
Dur
ing
a
boo
tfro
m
a
h
ard
r
es
et,
th
econ
figur
ati
o
n
o
fthes
e
p
in
si
s
u
n
af
fected.
No
te
:
W
h
en
t
h
eH
D
I16
i
sus
ed
fo
rboo
tin
g
or
o
ther
pu
rpo
ses
,bi
t0
is
th
eleast
sig
n
if
ican
t
b
it
an
d
n
o
tth
em
o
st
sig
n
if
ican
tb
it
as
fo
rot
h
er
DS
P
prod
uct
s.
T
a
bl
e
3
1
.
Re
s
e
tConfigu
ra
tion
Sign
a
ls
Signa
l
D
es
cript
ion
Setti
ngs
BM
[1–0]
D
e
te
rm
ines
boot
mode.
0
Boot
fr
om
HDI
16
por
t.
01
Boot
fr
om
I2
C.
1x
Reserv
ed.
SW
T
E
D
e
te
rm
ines
wat
c
hdog
funct
ionali
ty.
0
W
a
tc
hdog
t
ime
r
disab
led.
1
W
a
tc
hdog
time
r
enabled.
HDS
P
C
onf
igures
HDI
16
st
robe
polarit
y.
0
Host
Dat
a
s
trob
e
s
ac
tive
low
.
1
Host
Dat
a
s
trob
e
s
ac
tive
high.
H8
BI
T
C
onf
igures
HDI
16
operat
ion
mode.
0
HDI
16
port
c
onf
igured
fo
r16-
bi
top
erat
ion.
1
HDI
16
port
c
onf
igured
fo
r8-b
itope
rat
ion.
T
a
ble
3
2
.
Boot
M
ode
Se
tt
in
gs
BM
1
B
M
0
Boot
So
urce
0
Ext
e
rnal
ho
st
via
HDI
16
wit
h
t
h
e
P
LL
disabled.
01
I 2
C.
1
0
Ext
ernal
ho
st
via
the
HDI
1
6
wit
h
t
he
P
LL
enabled.
1
Reserv
ed.
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: MSC711XADS
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