- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄296572 > ML6692CH 100BASE-TX Physical Layer with MII PDF資料下載
參數(shù)資料
| 型號： | ML6692CH |
| 英文描述： | 100BASE-TX Physical Layer with MII |
| 中文描述： | 100BASE - TX的物理層與信息產(chǎn)業(yè)部 |
| 文件頁數(shù)： | 7/21頁 |
| 文件大?。?/td> | 325K |
| 代理商： | ML6692CH |
ML6692
15
Table 1. Initialization Interface Register
BIT(S)
NAME
DESCRIPTION
R/W
DEFAULT
I.15
PHY A4
PHY address bit 4
0
I.14
PHY A3
PHY address bit 3
0
I.13
PHY A2
PHY address bit 2
0
I.12
PHY A1
PHY address bit 1
0
I.11
PHY A0
PHY address bit 0
0
I.10
10HDUP
10BASE-T half duplex initialization bit
0
1 = 10BASE-T (half-duplex) capability
0 = no 10BASE-T (half-duplex) capability
I.9
10FDUP
10BASE-T full duplex initialization bit
0
1 = 10Mb/s full duplex capability
0 = no 10Mb/s full duplex capability
I.8
100T4
100BASE-T4 initialization bit
0
1 = 100BASE-T4 capability
0 = no 100BASE-T4 capability
I.7
ISODIS
Isolate bit disable (bit 0.10)
0
I.6
REPEATER
Repeater mode: when this bit is set to 1,
0
CRS isonly asserted when receiving non-idle
signal at TPINP/N, and the ML6692 is
forced to half duplex mode
I.5–I.0
Not used
Note: Bits I<10:8> are the values for bits 1.11, 1.12 and 1.15 and initial values for bits 4.5, 4.6 and 4.9 of the MII Management Interface.
INITIALIZATION INTERFACE REGISTER
MII MANAGEMENT INTERFACE REGISTERS
BIT(S)
NAME
DESCRIPTION
R/W
DEFAULT
0.15
Reset
1 = reset all register bits to defaults
R/W, SC
0
0 = normal operation
0.14
Loopback
1 = PMD loopback mode
R/W
0
0 = normal operation
0.13
Manual speed select
1 = 100Mb/s
R/W
1
(Active when 0.12 = 0)
0 = 10Mb/s
0.12
Auto negotiation enable
1 = enable auto negotiation
R/W
1
0 = disable auto negotiation
0.11
Power down
1 = power down
R/W
0
0 = normal operation
0.10
Isolate
1 = electrically isolate the ML6692 from MII
R/W
1
0 = normal operation
0.9
Restart auto negotiation
1 = restart auto negotiation
R/W, SC
0
0 = normal operation
0.8
Duplex mode
1 = Full duplex select, auto negotiation disabled
R/W
0
0 = Half duplex select, auto negotiation disabled
0.7
Collision Test
1 = enable COL signal test
R/W
0
0 = normal operation
0.6 – 0.0
Not Used
Table 2. Control Register
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ML6692CQ | 100BASE-TX Physical Layer with MII |
| ML6694CH | 100BASE-TX Physical Layer with 5-Bit Interface |
| ML6694CQ | XC95108-10TQ100C - NOT RECOMMENDED for NEW DESIGN |
| ML6695CQ | 100BASE-X Fiber Physical Layer With 5-bit Interface |
| ML925J40F-11 | 1610 nm, LASER DIODE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ML6692CQ | 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:100BASE-TX Physical Layer with MII |
| ML6694 | 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:100BASE-TX Physical Layer with 5-Bit Interface |
| ML6694CH | 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:100BASE-TX Physical Layer with 5-Bit Interface |
| ML6694CQ | 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:100BASE-TX Physical Layer with 5-Bit Interface |
| ML6695 | 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:100BASE-X Fiber Physical Layer With 5-bit Interface |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。