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參數(shù)資料
| 型號： | ML6652EH |
| 英文描述： | 10/100Mbps Ethernet Fiber and Copper Media Converter with Auto Negotiation |
| 中文描述： | 10/100Mbps以太網(wǎng)光纖收發(fā)器和銅具有自動協(xié)商 |
| 文件頁數(shù)： | 9/28頁 |
| 文件大?。?/td> | 196K |
| 代理商： | ML6652EH |
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ML6652
17
January 2002
Preliminary Datasheet
OPERATING MODES
TRANSPARENT or NON-TRANSPARENT Mode of
operation. Transparent Mode is the default mode of
operation for the ML6652 when DUPLEX input is VCC/
2. In this mode, the control circuit implements the
state diagrams of the Auto-Negotiation sub-layer
defined in clause 5 of TIA/EIA-785 standard. In general
the enabled Physical Media Attachment (PMA) at the
fiber optic output is the equivalent to the technology
detected at the twisted pair input and the enabled
PMA at the twisted pair output is the equivalent to the
technology detected at the fiber optic input. Of
course system auto negotiation causes both paths to
the greatest common denominator. The system
chooses the greatest common denominator in the
following order least to greatest:
a)
Half DUPLEX, 10Mbs
b)
Full DUPLEX, 10Mbs
c)
Half DUPLEX, 100Mbs
d)
Full DUPLEX, 100Mbs
Note: In transparent mode the ML6652 does not generate
information. It only takes the information from the link
partner on one side (without adding or remove any
information) and it translates it to the language of the link
partner of other side.
This mode is for use in networks that have Auto-
Negotiation capabilities on both copper and fiber sides.
The ML6652 follows the demands of the far end link
partners during the network Auto-Negotiation. Link
Integrity Warning (LIW) cannot be enabled in this mode.
6) Special case for the Non-Transparent Mode:
The ML6652 operates in this mode when all of the
following three conditions are met:
a)
Duplex input is a VCC or a 0 Volts (or the
equivalent Reg. 30 settings) AND
b)
Twisted Pair Link is Auto-Negotiation capable
AND
c)
Both 10Mbps and 100Mbps operation are enabled
by SPEED input at VCC/2 or by bits in
management register 30.
If the Fiber Optic Link Partner is Auto-Negotiation capable
the ML6652 will allow the fiber optic link partner to auto-
negotiate through the ML6652 to the twisted pair link
partner. In this special case the non-transparent mode acts
in the same way as the transparent mode. This is because
the self-generation of FLP bursts is suppressed by the
presence of the FLP bursts from the fiber link partner.
The ML6652 can be configured in two general ways:
1) Through the management interface, pins 16 (MDIO)
and 17 (MDC), all of the registers can be changed
after power-up. The management interface settings
override any power-up register settings.
a)
All internal registers may be used to:
i)
Set operating modes,
(1) FORCED 10Mbps only mode,
(2) FORCED 100Mbps only mode,
(3) NON-TRANSPARENT Half Duplex only
(4) NON-TRANSPARENT Full and Half
Duplex with Auto-Negotiation
(5) TRANSPARENT 10/100Mbps with Auto-
Negotiation
ii) Select interface configurations
(1) Both fiber and copper
iii) Special modes
(1) Power Down Mode
(2) Loopback Test Modes
(3) Transmitter Output Off Mode:
(4) Backup Link Mode (Pin 40)
iv) And read control information
2) Through configuration and control pins
Note: Pins 4 AD4LIW and 40 BCKPLINK are both
shared between a power-up read and a later control
function and thus appear in both lists. Pin 4 AD4LIW
is read and the condition latched to set register 30 bit
12 subsequently it is used as an unlatched address
pin. Pin 40 BCKPLINK is read and the condition
latched to set register 28 bit 1, subsequently it is used
as an output to drive a second ML6652 to provide
back up link.
a)
At power up the following pins are read and the
appropriate registers are set: (but with a limited
sub-set of the control afforded by the
management control registers.)
i)
Pin 7 (PECLTP)
ii) Pin 8 (PECLQU)
iii) Pin 25 (DUPLEX)
iv) Pin 27 (SPEED)
v)
Pin 4 (AD4LIW)
vi) Pin 40 (BCKLINK)
Note: These pins are typically read a few microseconds
after power-up, if they are tied to supplies that do not
track the ML6652 power improper results may occur. To
reduce the parts count, pins Pin 7 (PECLTP), Pin 8
(PECLQU), Pin 4 (AD4LIW), Pin 5 (AD 32) and Pin 6
(AD10) may be supplies from a common 20K
resistor
tree as shown on our evaluation boards schematics
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| ML6652EM | 制造商:RF Micro Devices Inc 功能描述:IC TXRX 5.8GHZ FSK 44-PLCC |
| ML6652RDK-02 | 制造商:Micro Linear Corp (RFMD Inc. ) 功能描述:Reference Design Kit, Bulk |
| ML6652RDK-03 | 制造商:Micro Linear Corp (RFMD Inc. ) 功能描述:ML6652CH and ML6652CM Reference Design Kit, Bulk |
| ML66592 | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:CMOS 16-bit microcontroller |
| ML6671 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
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