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參數(shù)資料
| 型號： | ML6652EH |
| 英文描述： | 10/100Mbps Ethernet Fiber and Copper Media Converter with Auto Negotiation |
| 中文描述： | 10/100Mbps以太網(wǎng)光纖收發(fā)器和銅具有自動協(xié)商 |
| 文件頁數(shù)： | 28/28頁 |
| 文件大?。?/td> | 196K |
| 代理商： | ML6652EH |
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ML6652
9
January 2002
Preliminary Datasheet
PIN DESCRIPTIONS (continued)
Pin No. Signal Name
I/O
Description
Figure 1. Twisted Pair Interface Mode Input Networks
1500pF
200
10
11
ML6652
From Input
Transformer Circuit
Pulse H1019 or equivalent
PECL/LVPECL Compatible Interface Mode:
PECL/LVPECL compatible interface positive and complementary inputs. These
inputs form a differential input pair that receives 100Base-FX, 100Base-SX,
FLNP Bursts, or 10Base-FL signal from a fiber optic PMD. The PMD outputs
should be AC coupled to these inputs with .1F capacitors. The common mode
voltage is set internally with ~1K
or so resistors from each input pin to an on-
chip voltage reference. The positive output of the PMD (high during the high-
light state) must connect to TPINP and the complementary output of the PMD
must connect to TPINN
37
REQSD
I
The two operating modes available for this pin are selected with the
configuration pin PECLQU or the configuration bit PECLQU <30.2>
Twisted Pair Interface Mode:
Equalizer bias resistor pin. An external resistor connected between this pin and
ground sets internal currents that control the receiver’s adaptive equalizer
transfer function. The recommended resistor value is 5K
, 1%
PECL/LVPECL Compatible Interface Mode:
This input pin is connected to the Signal Detect (SD) output of a fiber optic
PMD module. The voltage level at this pin is compared to the voltage level at
pin SDTH to determine the logic value. If it is lower, then the input at TPINP/
TPINN is rejected. If it is higher, then the input at TPINP/TPINN is passed to the
internal circuits
39
SDTH
I
The voltage at this pin is a single ended PECL/LVPECL reference. Refer to
description of SDFO and REQSD pins. This pin is not used if the TPINP/TPINN
interface or the FOINP/FOINN are not setup for PECL/LVPECL compatible
mode. In such a case, the SDTH pin should be set to VCC
21
IOUT
O
The two operating modes available for these pins are selected with the
configuration pin PECLQU or the configuration bit PECLQU <30.7>
22
IOUT#
O
Fiber Optic Interface Mode:
IOUT (pin 21) becomes the output connection to the cathode of an external
fiber optic LED. The output data is NRZI encoded 100Base-FX or 100Base-SX
symbols during 100Mbps mode, Manchester encoded 10Base-FL data or
OPT_IDL (10Base-FL idle signal) during 10Mbps mode, and FLNP Bursts during
Auto-Negotiation.
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