參數(shù)資料
型號(hào): ML6652EH
英文描述: 10/100Mbps Ethernet Fiber and Copper Media Converter with Auto Negotiation
中文描述: 10/100Mbps以太網(wǎng)光纖收發(fā)器和銅具有自動(dòng)協(xié)商
文件頁數(shù): 2/28頁
文件大?。?/td> 196K
代理商: ML6652EH
ML6652
10
January 2002
Preliminary Datasheet
IOUT# (pin 22) is optionally used to provide current peaking. If peaking is
implemented, a 1K
off-chip resistor should be connected to ground and a 1nF
capacitor connected to IOUT. These components determine the peaking
current waveform. When peaking is not used, IOUT# should connect to VCC
PECL/LVPECL Compatible Interface Mode:
PECL/LVPECL interface positive and complementary outputs. These outputs
form a differential current output pair that drives NRZI encoded 100Base-SX or
100Base-FX symbols during 100Mbps mode, Manchester encoded 10Base-FL
data or OPT_IDL during 10Mbps mode, and FLNP Bursts during Auto-
Negotiation. IOUT and IOUT# are loaded with external resistors to VCC and
AC coupled to the inputs of a fiber optic PMD module (refer to description of
RTOP pin). A resistor network may be needed to setup the common mode
voltage at the input pins of the PMD module
36
RTOP
O
Fiber optic LED or PECL/LVPECL driver bias resistor. An external resistor
connected between RTOP and ground sets a constant bias current for the single
ended LED driver or differential PECL/LVPECL driver circuitry. These output
currents depend on the operating mode.
The recommended external component values are:
Fiber Optic Interface mode: (1% resistors, +/- 10% currents)
Indicated is the current into pin IOUT during the High-Light state.
2.8K
between RTOP and ground for 50mA.
2K
between RTOP and ground for 70mA.
1.4K
between RTOP and ground for 100mA.
PECL/LVPECL Interface mode:
1.4K
, 1%, between RTOP and ground for 10mA tail current.
62
, 1%, between IOUT and VCC.
62
, 1%, between IOUT# and VCC.
Also AC coupled to PMD inputs
33
FOINP
I
The two operating modes available for these pins and are selected with the
configuration pin PECLQU or the configuration bit PECLQU <30.7>
32
FOINN
I
Fiber Optic Interface Mode:
Fiber optic quantizer positive and complementary inputs. FOINP is
capacitively coupled to the output of a fiber optic receiver, while FOINN is
capacitively coupled to the VCC of the fiber optic receiver. Recommended
capacitor values: 10nF, 5%. FOINP voltage must be higher during the “high
light” state than during the low-light state
PECL/LVPECL Compatible Interface Mode:
PECL/LVPECL interface positive and complementary inputs. These inputs form
a differential input pair that receives 100Base-FX, 100Base-SX, FLNP Bursts, or
10Base-FL signal from a fiber optic PMD. The PMD outputs are AC coupled to
these inputs with 10nF, 5% capacitors. The common mode voltage is set
internally with ~900
(or so) resistors from each input pin to an on-chip
voltage reference. FOINP voltage must be higher during the “high light” state
than during the low-light state
30
CQOS
Data quantizer offset cancellation loop capacitor. An external capacitor
between this pin and VCC determines the dominant pole of the offset
cancellation feedback loop. The recommended value is .1F, 10%
PIN DESCRIPTIONS (continued)
Pin No. Signal Name
I/O
Description
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