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    參數(shù)資料
    型號: MH16S72DAMD-8
    廠商: Mitsubishi Electric Corporation
    英文描述: 1207959552-BIT (16777216 - WORD BY 72-BIT)Synchronous DRAM
    中文描述: 1207959552位(16777216 - Word的72位)同步DRAM
    文件頁數(shù): 6/52頁
    文件大?。?/td> 1045K
    代理商: MH16S72DAMD-8
    MH16S72AMA -8,-10,-12
    1207959552-BIT (16777216 - WORD BY 72-BIT)SynchronousDRAM
    MITSUBISHI LSIs
    ( / 52 )
    6
    MITSUBISHI
    ELECTRIC
    5. Mar.1997
    Preliminary Spec.
    Some contents are subject to change without notice.
    MIT-DS-0128-0.0
    PIN FUNCTION
    Input
    Master Clock:All other inputs are referenced to the rising
    edge of CK
    CKE0
    Input
    Clock Enable:CKE controls internal clock.When CKE is
    low,internal clock for the following cycle is ceased. CKE is
    also used to select auto / self refresh. After self refresh
    mode is started, CKE E becomes asynchronous input.Self
    refresh is maintained as long as CKE is low.
    /S
    (/S0,/S2)
    Input
    Chip Select: When /S is high,any command means
    No Operation.
    /RAS,/CAS,/WE
    Input
    Combination of /RAS,/CAS,/WE defines basic commands.
    A0-11
    Input
    A0-11 specify the Row/Column Address in conjunction with
    BA.The Row Address is specified by A0-11.The Column
    Address is specified by A0-9.A10 is also used to indicate
    precharge option.When A10 is high at a read / write
    command, an auto precharge is performed. When A10 is
    high at a precharge command, both banks are precharged.
    BA0,1
    Input
    Bank Address:BA0,1 is not simply BA.BA specifies the
    bank to which a command is applied.BA0,1 must be set
    with ACT,PRE,READ,WRITE commands
    DQ0-63,CB0-7
    Input/Output
    Data In and Data out are referenced to the rising edge of
    CK
    DQMB0-7
    Input
    Din Mask/Output Disable:When DQMB is high in burst
    write.Din for the current cycle is masked.When DQMB is high
    in burst read,Dout is disabled at the next but one cycle.
    Vdd,Vss
    Power Supply Power Supply for the memory mounted module.
    SCL
    SDA
    SA0-3
    Input
    Output
    Input
    Serial clock for serial PD
    Serial data for serial PD
    Address input for serial PD
    CK
    (CK0 ~ CK3)
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