參數(shù)資料
型號(hào): MCF5470
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: MCF547x Integrated Microprocessor Electrical Characteristics
中文描述: MCF547x集成的微處理器,電氣特性
文件頁數(shù): 5/28頁
文件大?。?/td> 706K
代理商: MCF5470
Supply Voltage Sequencing and Separation Cautions
MCF547x Integrated Microprocessor Electrical Characteristics, Rev. 2
Freescale Semiconductor
5
4
Supply Voltage Sequencing and Separation
Cautions
Figure 3
shows situations in sequencing the I/O V
DD
(EV
DD
), SDRAM V
DD
(SD V
DD
), PLL V
DD
(PLL
V
DD
), and Core V
DD
(IV
DD
).
Figure 3. Supply Voltage Sequencing and Separation Cautions
The relationship between SD V
DD
and EV
DD
is non-critical during power-up and power-down sequences.
Both SD V
DD
(2.5V or 3.3V) and EV
DD
are specified relative to IV
DD
.
4.1
Power Up Sequence
If EV
DD
/SD V
DD
are powered up with the IV
DD
at 0V, then the sense circuits in the I/O pads will cause
all pad output drivers connected to the EV
DD
/SD V
DD
to be in a high impedance state. There is no limit
on how long after EV
DD
/SD V
DD
powers up before IV
DD
must power up. IV
DD
should not lead the EV
DD
,
SD V
DD
or PLL V
DD
by more than 0.4V during power ramp up, or there will be high current in the internal
ESD protection diodes. The rise times on the power supplies should be slower than 1 microsecond to avoid
turning on the internal ESD protection clamp diodes.
EV
DD
, SD V
DD
(3.3V)
SD V
DD
(2.5V)
IV
DD
, PLL V
DD
Supplies Stable
2
1
3.3V
2.5V
1.5V
0
Time
NOTES:
1.
IV
DD
should not exceed EV
DD
, SD V
DD
or PLL V
DD
by more than
0.4V at any time, including power-up.
Recommended that IV
DD
/PLL V
DD
should track EV
DD
/SD V
DD
up to
0.9V, then separate for completion of ramps.
Input voltage must not be greater than the supply voltage (EV
DD
, SD V
DD
,
IV
DD
, or PLL V
DD
) by more than 0.5V at any time, including during power-up.
Use 1 microsecond or slower rise time for all supplies.
2.
3.
4.
D
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