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參數(shù)資料
| 型號： | MC68HC08KX8DW |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁數(shù)： | 193/210頁 |
| 文件大?。?/td> | 1346K |
| 代理商： | MC68HC08KX8DW |
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Low-Power Modes
MC68HC908KX8 MC68HC908KX2 MC68HC08KX8 Data Sheet, Rev. 2.1
Freescale Semiconductor
83
period tolerance plus 10%) must be added. This adjustment can be reduced with trimming. Table 7-4
shows some typical values for settling time.
7.4.7 Trimming Frequency on the Internal Clock Generator
The unadjusted frequency of the low-frequency base clock (IBASE), when the comparators in the
frequency comparator indicate zero error, will vary as much as
±25% due to process, temperature, and
voltage dependencies. These dependencies are in the voltage and current references, the offset of the
comparators, and the internal capacitor. The voltage and temperature dependencies have been designed
to be a maximum of approximately
±1% error. The process dependencies account for the rest.
Fortunately, for an individual part, the process dependencies are constant. An individual part can operate
at approximately
±2% variance from its unadjusted operating point over the entire spec range of the
application. If the unadjusted operating point can be changed, the entire variance can be limited to
±2%.
The method of changing the unadjusted operating point is by changing the size of the capacitor. This
capacitor is designed with 639 equally sized units. 384 of these units are always connected. The
remaining 255 units are put in by adjusting the ICG trim factor (TRIM). The default value for TRIM is $80,
or 128 units, making the default capacitor size 512. Each unit added or removed will adjust the output
frequency by about
±0.195% of the unadjusted frequency (adding to TRIM will decrease frequency).
Therefore, the frequency of IBASE can be changed to
±25% of its unadjusted value, which is enough to
cancel the process variability mentioned before.
The best way to trim the internal clock is to use the timer to measure the width of an input pulse on an
input capture pin (this pulse must be supplied by the application and should be as long or wide as
possible). Considering the prescale value of the timer and the theoretical (zero error) frequency of the bus
(307.2 kHz *N/4), the error can be calculated. This error, expressed as a percentage, can be divided by
0.195% and the resultant factor added or subtracted from TRIM. This process should be repeated to
eliminate any residual error.
7.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
7.5.1 Wait Mode
The ICG remains active in wait mode. If enabled, the ICG interrupt to the CPU can bring the MCU out of
wait mode.
In some applications, low power consumption is desired in wait mode and a high frequency clock is not
needed. In these applications, reduce power consumption by either selecting a low-frequency external
clock and turn the internal clock generator off, or reduce the bus frequency by minimizing the ICG
multiplier factor (N) before executing the WAIT instruction.
Table 7-4. Typical Settling Time Examples
τ1
τ2
N
τ15
τtot
1/ (6.45 MHz)
1/ (25.8 MHz)
84
430
s
1165
s
1/ (25.8 MHz)
1/ (6.45 MHz)
21
107
s
840
s
1/ (25.8 MHz)
1/ (307.2 kHz)
1
141
s
875
s
1/ (307.2 kHz)
1/ (25.8 MHz)
84
11.9 ms
12.6 ms
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