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參數(shù)資料
| 型號(hào)： | MC34982PNA |
| 廠商： | 飛思卡爾半導(dǎo)體(中國(guó))有限公司 |
| 英文描述： | Single Intelligent High-Current Self-Protected Silicon High-Side Switch (2.0 mOhm)(單智能大電流帶自保護(hù)功能的硅高端開關(guān)（2mOhm）) |
| 中文描述： | 單智能大電流的自我保護(hù)硅高邊開關(guān)（2.0毫歐）（單智能大電流帶自保護(hù)功能的硅高端開關(guān)（2mOhm）） |
| 文件頁數(shù)： | 16/24頁 |
| 文件大?。?/td> | 771K |
| 代理商： | MC34982PNA |
33982
16
Go to: www.freescale.com
Figure 7. Single 8-Bit Word SPI Communication
Figure 8. Multiple 8-Bit Word SPI Communication
Serial Input Communication
SPI communication is accomplished using 8-bit messages.
A message is transmitted by the MCU starting with the MSB,
D7, and ending with the LSB, D0 (
Table 1
). Each incoming
command message on the SI terminal can be interpreted using
the following bit assignments: the MSB (D7) is the watchdog bit
and in some cases a register address bit; the next three bits,
D6–D4, are used to select the command register; and the
remaining four bits, D3–D0, are used to configure and control
the output and its protection features.
Multiple messages can be transmitted in succession to
accommodate those applications where daisy chaining is
desirable or to confirm transmitted data as long as the
messages are all multiples of eight bits. Any attempt made to
latch in a message that is not eight bits will be ignored.
The 33982 has defined registers, which are used to
configure the device and to control the state of the output.
Table 2
, page 17, summarizes the SI registers. The registers
are addressed via D6–D4 of the incoming SPI word (
Table 1
).
CSB
SI
SCLK
D7
D1
D2
D3
D4
D5
D6
D0
OD7
OD6
OD1
OD2
OD3
OD4
OD5
NOTES:
OD0
SO
1.
2.
3.
3. OD7–OD0 relate to the first 8 bits of ordered fault and status data out of the device.
of the device.
1.
RST
is a logic [1] state during the above operation.
2. D7–D0 relate to the most recent ordered entry of data into the device.
C S B
S I
SCLK
D 7
D 1 *
D 2 *
D 5 *
D 6 *
D 7 *
D 0
D 1
D 6
D 5
D 2
D 0 *
O D 5
O D 6
O D 7
D 6
D 7
O D 0
O D 1
O D 2
D 1
D 2
D 5
:
Notes
D 0
SO
1 .
3 .
3. D7*–D0* relate to the previous 8 bits (last command word) of data that was previously shifted into the device.
SI
RST
1.
RST
is a logic [1] state during the above operation.
2. D7–D0 relate to the most recent ordered entry of data into the device.
4. OD7–OD0 relate to the first 8 bits of ordered fault and status data out of the device.
Table 1. SI Message Bit Assignment
Bit Sig
SI Msg Bit
Message Bit Description
MSB
D7
Watchdog in: toggled to satisfy watchdog
requirements; also used as a register address
bit.
D6–D4
Register address bits.
D3–D1
Used to configure the inputs, outputs, and the
device protection features and SO status
content.
LSB
D0
Used to configure the inputs, outputs, and the
device protection features and SO status
content.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
n
.
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