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參數(shù)資料
| 型號： | MC33888FB |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 英文描述： | Quad High Side and Octal Low Side Switch for Automotive Applications(4高端開關(guān)及8低端開關(guān)，用于自動應用) |
| 中文描述： | 四高側(cè)和汽車應用八路低邊開關(guān)（4高端開關(guān)及8低端開關(guān)，用于自動應用） |
| 文件頁數(shù)： | 9/18頁 |
| 文件大?。?/td> | 711K |
| 代理商： | MC33888FB |
MC33888FB
Quad High Side and Octal Low Side Switch for Automotive
9
NOTES:
1. Upper and lower logic threshold voltage range applies to SI, CSB, SCLK, RSTB, IHS0-3, ILS, WAKE and WDIN input signals.The WAKE,
FSI, and RSTB signals are derived from an internal supply
2. Parameter is guaranteed by design but is not production tested.
3. Input capacitance of SI, CSB, SCLK, RSTB, IHS0-3, ILS, WAKE and WDIN. This parameter is guaranteed by process monitor but is not
production tested.
4. The current must be limited by a series resistance when using voltages higher than the WICV.
5. The CSB is pulled up to VDD.
POWER OUTPUT TIMING
Notes
1. For HS Output Rise and Fall time respectively, measured across a 5 Ohm resistive load at 10% to 90% voltage points. These parameters
are guaranteed by process monitor.
2. For LS Outputs, turn ON delay time measured from rising edge of CSB to 90% of output OFF Vout with RL=27 Ohm resistive load. For HS
Outputs, turn ON delay time measured from rising edge of CSB to 90% of output OFF Vout with RL=5 Ohm resistive load.
3. For LS Output, turn OFF delay time measured from rising edge of CSB to 10% of output OFF Vout voltage with RL=27 Ohm resistive load.
For HS Output, turn OFF delay time measured from rising edge of CSB to 10% of output OFF Vout voltage with RL=5 Ohm resistive load.
4. Propagation time of Short Fault Disable Report Delay measured from rising edge of CSB to Output disabled, LS=5.0V, and device config-
ured for LS output over current latchoff using CLOCCR.
5. Wdto delay measured from the rising edge of WAKE or RSTB from the sleep state, to the HS0,1 turn-on with the outputs driven OFF and
the FSI floating. The accuracy of wdto is maintained for all configured watchdog timeouts.
6. For LS Output Rise and Fall time respectively, measured across a 27 Ohm resistive load at 30% to 70% and 70% to 30% voltage points.
7. Tpct measured from the rising edge of CSB to 90% of HSxxilimpk when the peak current limit is enabled.
Input Logic Pulldown Resistor (WAKE, RSTB)
Rdwn
100
200
400
kOhm
Input Logic Pullup Current (CSB, FSI, Vin=3.5V) (Note 5)
Iup
5
20
uA
Wake Input Clamp Voltage ( WICI < 2.5mA) (Note 4)
WICV
7
14
V
Wake Input Forward Voltage (WICI = - 2.5mA)
WIFV
-2
-0.3
V
SO High State Output Voltage (IOH=1.0 mA)
VSOH
0.8VDD
V
FLTB, SO Low State Output Voltage (IOL=-1.6mA)
VSOL
0.2
0.4
V
SO Tri-State Leakage Current (CSB
≥
3.5V)
SOLK
-5
0
5
uA
Input Capacitance (Note 3)
Cin
4
12
pF
SO, FLTB Tri-State Capacitance (Note 2)
CSO
20
pF
HS Output Rising Slew Rate (Note 1)
SRr
0.1
0.3
1
V/uS
HS Output Falling Slew Rate (Note 1)
SRf
0.1
0.3
1
V/uS
LS & HS Output Turn ON delay Time (Note 2)
Tdly(on)
1.0
200
uS
LS & HS Output Turn OFF delay Time (Note 3)
Tdly(off)
1.0
200
uS
Direct Input Switching Frequecy
PWMf
125
Hz
LS Output Fault Delay Timer (Note 4)
Tdly(flt)
70
150
250
uS
Watchdog timeout (Note 5)
wdto
340
524
707
mS
LS Output Rise Time (Note 6)
LSrt
1
10
uS
LS Output Fall Time (Note 6)
LSft
1
10
uS
Peak Current Limit Timer (Note 7)
Tpct
40
70
100
mS
F
Freescale Semiconductor, Inc.
For More Information On This Product,
n
.
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