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參數(shù)資料
| 型號： | MC33888FB |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | Quad High Side and Octal Low Side Switch for Automotive Applications(4高端開關(guān)及8低端開關(guān)，用于自動應(yīng)用) |
| 中文描述： | 四高側(cè)和汽車應(yīng)用八路低邊開關(guān)（4高端開關(guān)及8低端開關(guān)，用于自動應(yīng)用） |
| 文件頁數(shù)： | 13/18頁 |
| 文件大?。?/td> | 711K |
| 代理商： | MC33888FB |
MC33888FB
SPI Interface and Protocol Description
Quad High Side and Octal Low Side Switch for Automotive
13
IHSx pin(s) with its (their) corresponding D0-D3 message bit(s) when addressing the SOCR. A logic H on any or all of the
D4-D11 bits will result in a Boolean AND of the ILS and the corresponding D4-D11 message bits when addressing the
SOCR. Similarly, a logic L on the D0-D3 pins will result in a Boolean OR of the IHSx pin(s) to their corresponding message
bits when addressing the SOCR, and the ILS will be Boolean ORed with message bits D4
–
D11 when addressing the
SOCR (if ILS enabled).
- Address LHH (Watchdog and Current Sense Configuration Register (WDCSCR))
–
This register is used by the master to con-
figure the Watchdog Timeout and the CSNS01 and CSNS23 pins. The Watchdog timeout is configured using bits D4 and
D5. The state of D4 and D5 determine the divided value of the wdto. For example, if D4 and D5 are logic LL, respectively,
then the wdto will be in the default state as specified in Table 10. A D4D5 of HL will result in a watchdog timeout of wdto
÷
2. Similarly, a D4D5 of LH results in a watchdog timeout of wdto
÷
4, and a D4D5 of HH results in a watchdog timeout of
wdto
÷
8. Note that when D4D5 bits are programmed for the desired watchdog timeout period, the WDSPI bit should be
toggled as well to insure that the new timeout period is programmed at the beginning of a new count sequence
.
CSNS01 is
the current sense output for the HS0 and HS1 outputs. Similarly, the CSNS23 pin is the current sense output for the HS2
and HS3 outputs respectively. In this mode, a logic H on any or all of the message bits that control the HS outputs will result
in the sensed current from the corresponding output to be directed out of the appropriate CSNS output. For example, if D0
and D1 are both logic H, then the sensed current from HS0 and HS1 will be summed into the CSNS01. If D2 is logic H and
D3 is logic L, then only the sensed current from HS2 will be directed out of CSNS23.
- Address HLL (Open Load Configuration Register (OLCR))
–
This register allows the master to configure each of the outputs for
Open Load Fault detection. While in this mode, a logic H on any of the D0-D3 message bits will disable the corresponding
outputs
’
circuitry that allows the device to detect open load faults while the output is off.
For the Low side drivers, a logic
H on any of the D4-D11 bits will enable the open load detection circuitry.
This feature allows the master to minimize
load current in some applications, and may be useful to diagnose output shorts to battery (for HS).
- Address HLH (Current Limit Over Current Configuration Register (CLOCCR)) - This register allows the master to individually
override the peak current limit levels for each of the High Side outputs. A logic H on any or all of the D0-D3 bit(s) results in
the corresponding HSx to current limit at the sustain current limit level. This register also allows the master to enable or dis-
able the over current shutdown of the Low Side outputs. A logic H on any or all ot the D4-D11 message bit(s) will result in
the corresponding LSxx to latch off if the current exceeds ILIM after a timeout of tdly(flt).
- Address HHL
–
Not presently used
- Address HHH
–
This register is reserved for test and is not accessible via SPI during normal operation.
Table 2
ADDRESS AND CONFIGURATION BIT MAP
HIGH-SIDE
LOW-SIDE
ADDRESS
WD
REG
NAME
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D
12
D
13
D
14
D
15
HS
0
HS
1
HS
2
HS
3
LS
4
LS
5
LS
6
LS
7
LS
8
LS
9
LS
10
LS
11
L
L
L
X
SOCR
PW
B0
PW
B1
PW
B2
PW
B3
PW
B4
PW
B5
PW
B6
PW
B7
PW
B8
PW
B9
PW
B10
PW
B11
L
L
H
X
DICR
A/
OB
0
A/
OB
1
A/
OB
2
A/
OB
3
A/
OB4
A/
OB
5
A/
OB
6
A/
OB
7
A/
OB8
A/
OB
9
A/
OB1
0
A/
OB1
1
L
H
L
X
LFCR
CS
0
CS
1
CS
2
CS
3
WD
L
WD
H
NA
NA
NA
NA
NA
NA
L
H
H
X
WDCSCR
OLB
0
OLB
1
OLB
2
OLB
3
OL
4
OL
5
OL
6
OL
7
OL
8
OL
9
OL
10
OL
11
H
L
L
X
OLCR
ILIM
0
ILIM
1
ILIM
2
ILIM
3
OC
4
OC
5
OC
6
OC
7
OC
8
OC
9
OC
10
OC
11
H
L
H
X
CLOCCR
-
-
-
-
-
-
-
-
-
-
-
-
H
H
L
X
NOT
USED
OT
ILIM
WD
ILIM
PK
H
H
H
X
TEST
F
Freescale Semiconductor, Inc.
For More Information On This Product,
n
.
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