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參數(shù)資料
| 型號： | MC33888FB |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 英文描述： | Quad High Side and Octal Low Side Switch for Automotive Applications(4高端開關及8低端開關，用于自動應用) |
| 中文描述： | 四高側(cè)和汽車應用八路低邊開關（4高端開關及8低端開關，用于自動應用） |
| 文件頁數(shù)： | 12/18頁 |
| 文件大?。?/td> | 711K |
| 代理商： | MC33888FB |
MC33888FB
SPI Interface and Protocol Description
Quad High Side and Octal Low Side Switch for Automotive
12
SI COMMUNICATION
SPI communication will be accomplished via 16bit messages. A message is transmitted by the master starting with the MSB
D15 and ending with the LSB D0. Each incoming command message on the SI pin can be interpreted using the following bit
assignment: the first twelve LSBs, D0-11, control each of the twelve outputs, the next three bits, D12-D14, determine the com-
mand mode, and the MSB, D15, is the watchdog bit (see TABLE 1). Multiple messages can be transmitted in succession to
accommodate those applications where daisy chaining is desirable, or to confirm transmitted data, as long as the messages are
all multiples of 16bits. If an attempt is made to latch in a message that is not 16bits, then it is ignored.
The QHSOLSS has 6 registers which are used to configure the device and control the state of the four high-side and eight low-
side outputs. The registers are addressed via D12-D14 of the incoming SPI word (see TABLE 1).
Table 1
SI MESSAGE BIT ASSIGNMENT
The eight possible addresses (D12,D13,D14) and a description of their impact on the device operation is as follows
(see TABLE 2):
- Address LLL (SPI Output Control Register (SOCR))
–
This register allows the master to control the outputs via the SPI. Incom-
ing message bits D0-3 reflect the desired states of the high-side outputs HS0-HS3. Message bits D4-D11 reflect the desired
state of the low-side outputs LS4-LS11 respectively.
- Address LLH (Direct Input Control Register (DICR)) -This register is used by the master to enable direct input control of the
outputs. For the outputs, a logic L on bits D0-D11 will enable the corresponding output for direct control. A logic H on a
D0-D11 bit will disable the output from direct control.
- Address LHL (Logic Function Control Register (LFCR))
–
This register is used by the master to configure the relationship
between the SOCR bits D0
–
D11 and the Direct Inputs IHSx and ILS. While addressing this register (if the Direct Inputs
were enabled for direct control with the DICR), a logic H on any or all of the D0-D3 bits will result in a Boolean AND of the
For More Information On This Product,
BIT
SIG
SI
MESSAGE
BIT
MESSAGE BIT DESCRIPTION
MSB
D15
Watchdog in: toggled to satisfy watchdog requirements
D14
Register Address Bit:
D13
Register Address Bit
D12
Register Address Bit
D11
Used to Configure Low-Side Output LS11
D10
Used to Configure Low-Side Output LS10
D9
Used to Configure Low-Side Output LS9
D8
Used to Configure Low-Side Output LS8
D7
Used to Configure Low-Side Output LS7
D6
Used to Configure Low-Side Output LS6
D5
Used to Configure Low-Side Output LS5 (Watchdog timeout MSB during
WDCSCR configuration)
D4
Used to Configure Low-Side Output LS4 (Watchdog timeout LSB during
WDCSCR configuration)
D3
Used to Configure High-Side Output HS3
D2
Used to Configure High-Side Output HS2
D1
Used to Configure High-Side Output HS1
LSB
D0
Used to Configure High-Side Output HS0
F
Freescale Semiconductor, Inc.
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