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參數(shù)資料
| 型號(hào)： | MC33888FB |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | Quad High Side and Octal Low Side Switch for Automotive Applications(4高端開關(guān)及8低端開關(guān)，用于自動(dòng)應(yīng)用) |
| 中文描述： | 四高側(cè)和汽車應(yīng)用八路低邊開關(guān)（4高端開關(guān)及8低端開關(guān)，用于自動(dòng)應(yīng)用） |
| 文件頁數(shù)： | 11/18頁 |
| 文件大?。?/td> | 711K |
| 代理商： | MC33888FB |
MC33888FB
SPI Interface and Protocol Description
Quad High Side and Octal Low Side Switch for Automotive
11
The SPI interface has full duplex, three wire synchronous data transfer and has four I/O lines associated with it: (SI, SO, SCLK,
and CSB). The SI/SO pins of the QHSOLSS follow a first in / first out (D15 / D0) protocol with both input and output words trans-
ferring the most significant bit first. All inputs are compatible with 5.0 V CMOS logic levels. During SPI output control, a logic L
in a message word will result in the designated output being turned off. Similarly, a logic H will turn on a corresponding output.
All specific pin functions are specified as follows:
SCLK
–
Clocks the internal shift registers of the QHSOLSS. The Serial Input (SI) pin accepts data into the input shift register on
the falling edge of the SCLK signal while the serial output pin (SO) shifts data information out of the SO Line Driver on the
rising edge of the SCLK signal. It is important that the SCLK pin be in a logic low state whenever the Chip Select Bar (CSB)
makes any transition. For this reason, it is recommended that the SCLK pin be kept in a logic L as long as the device is not
accessed (CSB in logic H state). SCLK has an internal pull-down
“
Idwn
”
. When CSB is logic H, signals at the SCLK and
SI pins are ignored and SO is tri-stated (high impedance). See the Data Transfer Timing diagram in Figure 2.
SI
–
This pin is the input of Serial Instruction data. SI information is read in on the falling edge of SCLK. A sixteen bit stream of
serial data is required on the SI pin, starting with D15, D14, etc, to D0. The twelve outputs of the QHSOLSS are configured
and controlled using the 3 bit addressing scheme and the twelve assigned data bits designed into the QHSLOSS. SI has
an internal
pulldown
“
Idwn
”
.
SO
–
The Serial Output data pin is a tri-stateable output from the shift register. The SO pin remains in a high impedance state
until the CSB pin is put into a logic L state. The SO data report the status of the outputs as well as provide the capability to
reflect the state of the direct inputs. The SO pin changes states on the rising edge of SCLK and reads out on the falling
edge of SCLK. When an output is on or off and not faulted, the corresponding SO bit, OD0
–
OD11, are a logic L. If the out-
put is faulted, the corresponding SO state is a logic H. SO OD12-OD14 reflect the state of six various inputs (three at a
time) depending upon the reported state of the previously written watchdog bit OD15.
CSB
–
The Chip Select (Bar) pin enables communication with the Master device. When this pin is in a logic L state, the
QHSOLSS is capable of transferring information to and receiving information from the Master. The QHSOLSS latches in
data from the input shift registers to the addressed registers on the rising edge of CSB. The QHSOLSS transfers status
information from the power outputs to the shift registers on the falling edge of CSB. The output driver on the SO pin is
enabled when CSB is logic L. CSB is only transitioned from a logic H state to a logic L state when SCLK is a logic L. CSB
has an internal pullup
“
Iup
”
.
The QHSOLSS is capable of interfacing directly with a microcontroller, via the 16 bit SPI protocol described and specified below
Figure 2. Data Transfer Timing
.
FIGURE 2. DATA TRANSFER TIMING
Fi
C S B
S I
S C LK
SO
D 0
D 14
D 13
D 12
D 11
D 10
D 9
D 8
D 7
D 6
D 1
D 2
D 3
D 4
D 5
O D 3
D 15
O D 2
O D 1
O D 0
O D 9
O D 8
O D 7
O D 6
O D 5
O D 4
O D 14
O D 13
O D 12
O D 11
O D 10
1.
2.
3.
R S TB is in a logic H state during the above operation.
D O , D 1, D 2, ... , and D 15 relate to the m ost recent ordered entry of program data into the Q H S LO S S
O D 0, O D 1, O D 2, ..., and O D 15 relate to the first 16 bits of ordered fault and status data out of the Q HS LO SS
FIG U R E 2a. SIN G LE 16bit W O R D SP I C O M M U N IC A T IO N
N O T E S:
O D 15
C S B
S I
S C L K
S O
D 0
D 1 4 *
D 1 3 *
D 2 *
D 1 *
D 0 *
D 1 5
D 1 4
D 1
D 2
D 1 3
D 1 5 *
D 2 *
D 1 *
D 0 *
O D 2
O D 0
D 1 5 *
D 1 4 *
D 1 3 *
O D 1 4
O D 1 3
O D 3
1 .
2 .
3 .
4 .
R S T B is in a lo g ic H sta te d u rin g th e a b o ve o p e ra tio n .
D O , D 1 , D 2 , ... , a n d D 1 5 re la te to th e m o st re c e n t o rd e re d e n try o f p ro g ram d ata in to th e Q H S L O S S
O D 0 , O D 1 , O D 2 , ..., a n d O D 1 5 re la te to th e firs t 1 6 b its o f o rd e re d fa u lt a n d s tatu s d a ta o u t o f th e Q H S L O S S
N O T E S
:
O D 1 5
F
Freescale Semiconductor, Inc.
For More Information On This Product,
n
.
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