參數(shù)資料
型號(hào)： MB9AF112MPMC
元件分類： 微控制器/微處理器
英文描述： RISC MICROCONTROLLER, PQFP80
封裝： 0.50 MM PITCH, PLASTIC, LQFP-80
文件頁(yè)數(shù)： 93/112頁(yè)
文件大?。?/td> 1225K
代理商： MB9AF112MPMC
81
FUJITSU SEMICONDUCTOR CONFIDENTIAL
r2.1
MB9A110 Series
DS706-00011-1v0-E
Synchronous serial(SPI = 0, SCINV = 1)
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)
Vcc < 4.5V
Vcc ≥ 4.5V
Parameter
Symbol
Pin
name
Conditions
Min
Max
Min
Max
Unit
Serial clock cycle time
tSCYC SCKx
4tcycp
-
4tcycp
-
ns
SCK ↑ → SOT delay time
tSHOVI
SCKx
SOTx
-30
+30
- 20
+ 20
ns
SIN → SCK ↓ setup time
tIVSLI
SCKx
SINx
50
-
30
-
ns
SCK ↓ → SIN hold time
tSLIXI
SCKx
SINx
Internal shift
clock
operation
0
-
0
-
ns
Serial clock "L" pulse width
tSLSH
SCKx
2tcycp
- 10
-
2tcycp -
10
-
ns
Serial clock "H" pulse width
tSHSL
SCKx
tcycp +
10
-
tcycp +
10
-
ns
SCK ↑ → SOT delay time
tSHOVE
SCKx
SOTx
-
50
-
30
ns
SIN → SCK ↓ setup time
tIVSLE
SCKx
SINx
10
-
10
-
ns
SCK ↓ → SIN hold time
tSLIXE
SCKx
SINx
20
-
20
-
ns
SCK fall time
tF
SCKx
-
5
-
5
ns
SCK rise time
tR
SCKx
External shift
clock
operation
-
5
-
5
ns
Notes:
The above characteristics apply to CLK synchronous mode.
tCYCP indicates the APB bus clock cycle time. Please see the block diagram to refer the APB bus
number which UART is connected.
These characteristics only guarantee the same relocate port number.
For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance = 30pF.
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PDF描述
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