參數(shù)資料
型號: MAX9693ESE
廠商: Maxim Integrated Products
文件頁數(shù): 10/12頁
文件大?。?/td> 0K
描述: IC COMPARATOR W/LE 16-SOIC
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 50
類型: 帶鎖銷
元件數(shù): 2
輸出類型: 補充型,ECL
電壓 - 輸入偏移(最小值): 6.5mV @ 5V
電流 - 輸入偏壓(最小值): 20µA @ 5V
電流 - 輸出(標準): 50mA
電流 - 靜態(tài)(最大值): 46mA
CMRR, PSRR(標準): 80dB CMRR,60dB PSRR
傳輸延遲(最大): 1.8ns
工作溫度: -40°C ~ 85°C
封裝/外殼: 16-SOIC(0.154",3.90mm 寬)
安裝類型: 表面貼裝
包裝: 管件
其它名稱: Q1130833G
MAX9691/MAX9692/MAX9693
The timing diagram (Figure 3) illustrates the series of
events that complete the compare function, under
worst-case conditions. The top line of the diagram illus-
trates two latch-enable pulses. Each pulse is high for
the compare function and low for the latch function. The
first pulse demonstrates the compare function; part of
the input action takes place during the compare mode.
The second pulse demonstrates a compare function
interval during which there is no change in the input.
The leading edge of the input signal (illustrated as a
large-amplitude, small-overdrive pulse) switches the
comparator after time interval tpd. Output Q and Q tran-
sistors are similar in timing. The input signal must occur
at time ts before the latch falling edge, and must be
maintained for time th after the edge to be acquired.
After th, the output is no longer affected by the input sta-
tus until the latch is again strobed. A minimum latch
pulse width of tpw(LE) is needed for the strobe opera-
tion, and the output transitions occur after a time tLE(±).
The MAX9691/MAX9692/MAX9693 will not false trip
(i.e., output invert) if one of the inputs is in the valid
common-mode range while the other input is outside
the common-mode range.
LATCH
ENABLE
DIFFERENTIAL
INPUT
VOLTAGE
Q
LATCH
COMPARE
ts
th
VOD
VIN
tLE(+)
VOS
50%
tpw(LE)
tpd
Figure 3. Timing Diagram
Single/Dual, Ultra-Fast, ECL-Output
Comparators with Latch Enable
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