參數(shù)資料
型號: MAX9526AEI/V+T
廠商: Maxim Integrated Products
文件頁數(shù): 26/38頁
文件大?。?/td> 0K
描述: IC VID DECODER NTSC/PAL 28QSOP
其它有關文件: Automotive Product Guide
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,500
類型: 視頻解碼器
應用: 車載系統(tǒng),播放器,電視
電壓 - 電源,模擬: 1.8V
電壓 - 電源,數(shù)字: 1.8V
安裝類型: 表面貼裝
封裝/外殼: 28-SSOP(0.154",3.90mm 寬)
供應商設備封裝: 28-QSOP
包裝: 帶卷 (TR)
Low-Power, High-Performance
NTSC/PAL Video Decoder
Disable Digital Anti-Aliasing Filter (DISAAFLT)
Disable the digital anti-aliasing filter following the ADC.
1 = Disables filter.
0 = Enables filter (default).
Sync Slicing Level (SSLICE)
Sets the sync slicing level.
1111 = Slice at 240 (decimal), near the blanking level.
1000 = Slice at 128 (decimal), near the center of the
sync (default).
0100 = Slice at 64 (decimal), about 25% of the sync.
0000 = Slice at 0 (decimal), near the bottom of the
sync.
All values between 0000 and 1111 are valid.
REG
B7
B6
B5
B4
B3
B2
B1
B0
0x0E
0
LLC_MODE
PLLBYP
PLLBW
PLL Control Register
REG
B7
B6
B5
B4
B3
B2
B1
B0
0x0F
0
DISAAFLT
1
SSLICE
Miscellaneous Register
Line-Locked Clock Mode (LLC_MODE)
0X = Async mode or line-locked mode is set automati-
cally (default).
10 = PLL is forced to line-locked mode.
11 = PLL is forced to async mode.
PLL Bypass Mode (PLLBYP)
When PLLBYP = 1, the ADC and the decoder use the
input crystal or clock (XTAL/OSC, XTAL2) directly.
1 = Bypass the PLL.
0 = PLL is enabled (default).
Line-Locked PLL Tracking Speed (PLLBW)
PLLBW controls a digital loop filter that sets the band-
width of the line-locked PLL.
000 = 180Hz
001 = 250Hz
010 = 375Hz
011 = 500Hz (default)
100 = 750Hz
101 = 1kHz
110 = 1.5kHz
111 = 2kHz
CB359
SA
V(FF)
SA
V(00)
SA
V(00)
SA
V(xy)
CB0
Y0
CR0
Y718
CR359
Y719
EA
V(FF)
EA
V(00)
EA
V(00)
EA
V(XY)
BLANK
LLC
D9–D2
HS
2 CLK
1 CLK
VS = 1
VS = 0
2 CLK
Figure 18. Horizontal and Vertical Sync Timing
MAX9526
32
Maxim Integrated
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