參數(shù)資料
型號: MAX5122BEEE
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: DAC
英文描述: +5V/+3V, 12-Bit, Serial, Force/Sense DACs with 10ppm/∑C Internal Reference
中文描述: SERIAL INPUT LOADING, 20 us SETTLING TIME, 12-BIT DAC, PDSO16
封裝: 0.150 INCH, 0.025 INCH PITCH, QSOP-16
文件頁數(shù): 14/20頁
文件大?。?/td> 285K
代理商: MAX5122BEEE
M
+5V /+3V, 12-Bit, S erial, Forc e/S ense DACs
with 10ppm/°C Internal Referenc e
14
______________________________________________________________________________________
S erial Data Output
The contents of the internal shift-register are output
serially on DOUT which allows for daisy-chaining of
multiple devices (see Applications Information as well
as data readback. The MAX5122/MAX5123 may be
programmed to shift data out of DOUT on the serial
clock’s rising edge (Mode 1) or on the falling edge
(Mode 0). The latter is the default during power-up and
provides a lag of 16 clock cycles, maintaining SPI,
QSPI, MICROWIRE, and PIC16/PIC17 compatibility. In
Mode 1, the output data lags DIN by 15.5 clock cycles.
During power-down, DOUT retains its last digital state
prior to shutdown.
User-Programmable Output (UPO)
The UPO feature allows an external device to be con-
trolled through the serial-interface setup (Table 1) there-
by reducing the number of microcontroller I/O ports
required. During power-down, this output will retain the
last digital state before shutdown. With
CLR
pulled low,
UPO will reset to the default state after wake-up.
Table 3. Detailed SSPCON Register Contents
Receive Overflow Detect Bit
Synchronous Serial Port Enable Bit.
0: Disables serial port and configures these pins as I/O port pins.
1: Enables serial port and configures SCK, SDO and SCI as serial-
port pins.
X
SSPOV
BIT6
BIT7
Clock Polarity Select Bit. CKP = 0 for SPI master-mode selection.
0
0
CKP
SSPM3
BIT4
BIT3
BIT5
1
SSPEN
0
0
SSPM2
SSPM1
BIT2
BIT1
1
SSPM0
BIT0
CONTROL BIT
Write Collision Detection Bit
X
WCOL
SYNCHRONOUS SERIAL-PORT CONTROL REGISTER
(SSPCON)
MAX5122/MAX5123
SETTINGS
Synchronous Serial Port Mode Select Bit. Sets SPI master mode
and selects f
CLK
= f
OSC
/ 16
X = Don’t care
Table 4. Detailed SSPSTAT Register Contents
X = Don’t care
SPI Clock Edge Select Bit. Data will be transmitted on the rising
edge of the serial clock.
1
CKE
BIT6
Buffer Full Status Bit
BIT7
Update Address
Read/Write Bit Information
Stop Bit
Start Bit
X
X
P
S
BIT4
BIT3
BIT5
Data Address Bit
X
D/A
X
X
R/W
UA
BIT2
BIT1
X
BF
BIT0
CONTROL BIT
SPI Data Input Sample Phase. Input data is sampled at the mid-
dle of the data output time.
0
SMP
SYNCHRONOUS SERIAL-PORT CONTROL REGISTER
(SSPSTAT)
MAX5130/MAX5131
SETTINGS
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