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參數(shù)資料
| 型號： | MAQ31751FXXXX |
| 廠商： | DYNEX SEMICONDUCTOR LTD |
| 元件分類： | 存儲控制器/管理單元 |
| 英文描述： | 16-BIT, 256 PAGES, MEMORY MANAGEMENT UNIT, QFP68 |
| 封裝： | QFP-68 |
| 文件頁數(shù)： | 15/18頁 |
| 文件大?。?/td> | 166K |
| 代理商： | MAQ31751FXXXX |
MA31751
6/18
4.1 SIGNAL DEFINITIONS
Pin Name
Function
Description
A00-A15
Processor Address Bus
An active-high address bus for addresses and XIO commands. A15 is the
LSB.
D00-D16
System Data Bus
Data bus used to transfer data to and from the MMU/BPU. D15 is the LSB and
D16 is the parity bit.
EA00-EA10
Extended Address Bus
If the MMU is selected (using CSN) then EA0-EA10 provides the system
extended address. EA3-EA10 should be combined with A4-A15 from the
processor to give the full 20 bit 1750A system address bus and EA0-EA10
with A4-A15 gives a 23 bit 1750B system address bus. (See Fig 4).During XIO
transfers, EA7-10 mimic A0-A3 to present the full processor address to the
system. When the MMU is not selected, EA0-EA10 become inputs to allow the
BPU to protect the appropriate section of extended memory.
ASIN
Address Strobe In
The rising edge of this active-high signal generated by the CPU or DMA
controller, indicates that a valid address is present on the MA31750.
DSN
Data Strobe
The rising edge of this active-low signal generated by the CPU or DMA
controller, indicates that valid data is present on D00-D16 of the MA31750.
EAS
Extended Address Strobe
The rising edge of this active-high signal indicates that a valid and stable
extended address is available from the MA31751. This pin becomes an input
when no MMU is selected and should be driven from the system address
strobe. During XIO cycles, EAS follows ASIN.
MION
Memory / IO Select
This input is used to select between normal operation and command transfer
(XIO) mode. A high indicates memory whilst a low indicates IO. This signal is
provided by the CPU or the DMA controller.
RDWN
Read / Write Select
This input indicates the direction of data transfer on the data bus. A high level
indicates that the processor is reading the bus whilst a low level indicates that
the processor is driving the bus. The input is driven by the CPU or the DMA
controller.
OIN
Operand / Instruction Select This input indicates the type of data on the data bus. A high indicates operand
data whilst a low indicates the presence of instruction data. The signal is
provided by the CPU or the DMA controller.
AS0-AS3
Address State
This bus comes from the DMA controller during DMA accesses. It is used by
the MMU as part of the page selection operation. (During CPU operation, this
information is read from the MMU’s copy of the CPU status word). If no MMU
function is required, these inputs should be tied to ground.
PS0-PS3
Processor State
This bus comes from the DMA controller during DMA accesses. It is used by
the MMU to provide lock and key protection on page accesses. (During CPU
operation, this information is read from the MMU’s copy of the CPU status
word.) If no MMU function is required, these inputs should be tied to ground.
SYSTEM BUSSES
BUS CONTROL
EXTENDED MEMORY CONTROL
Figure 6: Pin Description Table
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