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參數(shù)資料
| 型號(hào)： | M95320-WDW6TG |
| 廠商： | NUMONYX |
| 元件分類： | PROM |
| 英文描述： | 4K X 8 FLASH 2.7V PROM, PDSO8 |
| 封裝： | 0.169 INCH, ROHS COMPLIANT, TSSOP-8 |
| 文件頁數(shù)： | 3/45頁 |
| 文件大?。?/td> | 440K |
| 代理商： | M95320-WDW6TG |
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M95320, M95640, M95320-x, M95640-x
Operating features
4
Operating features
4.1
Supply voltage (VCC)
4.1.1
Operating supply voltage VCC
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [VCC(min), VCC(max)] range must be applied (see Table 8.). In order to
secure a stable DC supply voltage, it is recommended to decouple the VCC line with a
suitable capacitor (usually of the order of 10nF to 100nF) close to the VCC/VSS package
pins.
This voltage must remain stable and valid until the end of the transmission of the instruction
and, for a Write instruction, until the completion of the internal write cycle (tW).
4.1.2
Power-up conditions
When the power supply is turned on, VCC rises from VSS to VCC. During this time, the Chip
Select (S) is not allowed to float but must follow the VCC voltage, therefore the S line should
be connected to VCC via a suitable pull-up resistor.
In addition, the Chip Select (S) input offers a built-in safety feature, as the S input is edge
sensitive as well as level sensitive: after Power-up, the device does not become selected
until a falling edge has first been detected on Chip Select (S). This ensures that Chip Select
(S) must have been High, prior to going Low to start the first operation.
The VCC rise time must not be faster than 1V/s.
4.1.3
Internal device Reset
In order to prevent inadvertent Write operations during Power-up, a Power On Reset (POR)
circuit is included. At Power-up (continuous rise of VCC), the device will not respond to any
instruction until VCC has reached the Power On Reset threshold voltage (this threshold is
lower than the minimum VCC operating voltage defined in Tables XX).
When VCC has passed the POR threshold, the device is reset and in the following state:
●
Standby Power mode
●
deselected (at next Power-up, a falling edge is required on Chip Select (S) before any
instructions can be started).
●
not in the Hold Condition
Status Register state:
●
the Write Enable Latch (WEL) is reset to 0
●
Write In Progress (WIP) is reset to 0. The SRWD, BP1 and BP0 bits of the Status
Register are in the same state as when the power was last removed (they are non-
volatile bits).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M95320-WDW6TG/P | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:32 Kbit serial SPI bus EEPROMs with high-speed clock |
| M95320-WDW6TG/PC | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:32 Kbit serial SPI bus EEPROMs with high-speed clock |
| M95320WDW6TP | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:32 Kbit and 64 Kbit serial SPI bus EEPROMs with high-speed clock |
| M95320-WDW6TP | 功能描述:電可擦除可編程只讀存儲(chǔ)器 2.5 V to 5.5V 32k RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| M95320-WDW6TP/P | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:32 Kbit serial SPI bus EEPROMs with high-speed clock |
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