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參數(shù)資料
| 型號： | M95320-WDW6TG |
| 廠商： | NUMONYX |
| 元件分類： | PROM |
| 英文描述： | 4K X 8 FLASH 2.7V PROM, PDSO8 |
| 封裝： | 0.169 INCH, ROHS COMPLIANT, TSSOP-8 |
| 文件頁數(shù)： | 15/45頁 |
| 文件大小： | 440K |
| 代理商： | M95320-WDW6TG |
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Instructions
M95320, M95640, M95320-x, M95640-x
6.6
Write to Memory Array (WRITE)
As shown in Figure 12, to send this instruction to the device, Chip Select (S) is first driven
Low. The bits of the instruction byte, address byte, and at least one data byte are then
shifted in, on Serial Data Input (D).
The instruction is terminated by driving Chip Select (S) High at a byte boundary of the input
data. In the case of Figure 12, this occurs after the eighth bit of the data byte has been
latched in, indicating that the instruction is being used to write a single byte. The self-timed
the end of which the Write in Progress (WIP) bit is reset to 0.
If, though, Chip Select (S) continues to be driven Low, as shown in Figure 13, the next byte
of input data is shifted in, so that more than a single byte, starting from the given address
towards the end of the same page, can be written in a single internal Write cycle.
Each time a new data byte is shifted in, the least significant bits of the internal address
counter are incremented. If the number of data bytes sent to the device exceeds the page
boundary, the internal address counter rolls over to the beginning of the page, and the
previous data there are overwritten with the incoming data. (The page size of these devices
is 32 bytes).
The instruction is not accepted, and is not executed, under the following conditions:
●
if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable
instruction just before)
●
if a Write cycle is already in progress
●
if the device has not been deselected, by Chip Select (S) being driven High, at a byte
boundary (after the eighth bit, b0, of the last data byte that has been latched in)
●
if the addressed page is in the region protected by the Block Protect (BP1 and BP0)
bits.
Figure 12.
Byte Write (WRITE) sequence
1.
Depending on the memory size, as shown in Table 6, the most significant address bits are Don’t Care.
C
D
AI01795D
S
Q
15
2
1
3456789 10
20 21 22 23 24 25 26 27
14 13
3210
28 29 30
High Impedance
Instruction
16-Bit Address
0
765432
0
1
Data Byte
31
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M95320-WDW6TG/P | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:32 Kbit serial SPI bus EEPROMs with high-speed clock |
| M95320-WDW6TG/PC | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:32 Kbit serial SPI bus EEPROMs with high-speed clock |
| M95320WDW6TP | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:32 Kbit and 64 Kbit serial SPI bus EEPROMs with high-speed clock |
| M95320-WDW6TP | 功能描述:電可擦除可編程只讀存儲器 2.5 V to 5.5V 32k RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| M95320-WDW6TP/P | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:32 Kbit serial SPI bus EEPROMs with high-speed clock |
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