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參數(shù)資料
| 型號： | M72DW64000B90ZT |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 64Mbit (x8/ x16, Multiple Bank, Boot Block) Flash Memory and 16Mbit Pseudo SRAM, 3V Supply, Multiple Memory Product |
| 中文描述： | 64兆比特（x8 / x16插槽，多銀行，引導(dǎo)塊）和16Mbit的閃存?zhèn)戊o態(tài)存儲器，3V電源，多記憶體產(chǎn)品 |
| 文件頁數(shù)： | 8/19頁 |
| 文件大小： | 102K |
| 代理商： | M72DW64000B90ZT |
M72DW64000B
8/19
FUNCTIONAL DESCRIPTION
The Flash Memory and PSRAM components have
a common power supply. The components are dis-
tinguished by four chip enable inputs: E
F
for the
Flash memory, and E1
P
and E2
P
for the PSRAM.
Recommended operating conditions do not allow
more than one component (Flash Memory or
PSRAM) to be in active mode at the same time.
The most common example is simultaneous read
operations on the Flash Memory and PSRAM
components which would result in a data bus con-
tention. Therefore it is recommended, when read-
ing from one memory component, to put the other
in the high impedance state (see Table 2 Main Op-
eration Modes for details).
Table 2. Main Operation Modes
Note: 1. X = Don’t Care (V
IL
or V
IH
).
2. UB
P
and LB
P
are tied together.
3. This table is valid when BYTE = V
IH
. This table is also valid when BYTE = V
IL
, with the only difference that DQ15-DQ8 are always
high impedance when the Flash Memory components are being accessed.
4. For the Block Protect and Unprotect features, refer to the M29DW640D datasheet. Only the In-System Technique is available in
the stacked product.
5. To read the Manufacturer Code, the Device Code, the Block Protection Status and the Extended Block indicator bit, refer to the
“Auto Select Command” in the M29DW640D datasheet.
Operation Mode
(3)
E
F1
RP
F
G
W
E1
P
E2
P
UB
P
, LB
P(2)
DQ15-DQ0
F
Read
V
IL
V
IH
V
IL
V
IH
PSRAM must be in Standby
Flash Memory Data
Output
Write
V
IL
V
IH
V
IH
V
IL
Flash Memory Data
Input
Output Disable
X
V
IH
V
IH
V
IH
Any PSRAM mode is allowed
Flash Memory Hi-Z
Standby
V
IH
V
CC
±0.3
X
X
Reset
X
V
IL
X
X
P
Read
Flash Memory
must be in
Standby
V
IL
V
IH
V
IL
V
IH
V
IL
PSRAM Data Output
Write
V
IH
V
IL
V
IL
V
IH
V
IL
PSRAM Data Input
Output Disable
Any Flash
Memory mode
is allowable
V
IH
V
IH
V
IL
V
IH
X
PSRAM Hi-Z
Standby
X
X
V
IH
V
IH
X
Deep Power Down
X
X
X
V
IL
X
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