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參數(shù)資料
| 型號(hào)： | M7020R |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 32K x 68-bit Entry NETWORK SEARCH ENGINE |
| 中文描述： | 32K的× 68位進(jìn)入網(wǎng)絡(luò)搜索引擎 |
| 文件頁(yè)數(shù)： | 99/150頁(yè) |
| 文件大?。?/td> | 996K |
| 代理商： | M7020R |
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M7020R
Table 44. Latency of SEARCH from Cycles C and D to SRAM Access Cycle, 272-bit, Up to 8 Devices
Table 45. Shift of SSF and SSV from SADR
272-bit Search on Tables Configured as x272 Using Up to 31 M7020R Devices
The hardware diagram of the search subsystem of
31 devices is shown in Figure 71, page 101. Each
of the four blocks in the diagram represents a
block of eight M7020R devices, except the last
which has seven devices.The diagram for a block
of eight devices is shown in Figure 72, page 102.
The following are the parameters programmed
into the 31 devices.
– First thirty devices (devices 0–29):
CFG = 10101010, TLSZ = 10, HLAT = 000,
LRAM = 0, and LDEV = 0.
– Thirty-first device (device 30):
CFG = 10101010, TLSZ = 10, HLAT = 000,
LRAM = 1, and LDEV = 1.
Note:
All 31 devices must be programmed with the
same value of TLSZ and HLAT. Only the last de-
vice in the table must be programmed with
LRAM = 1 and LDEV = 1 (Device 30 in this case).
All other upstream devices must be programmed
with LRAM = 0 and LDEV = 0 (Devices 0 through
29 in this case).
The timing diagrams referred to in this paragraph
reference the HIT/MISS assumptions defined in
Table 46, page 101. For the purpose of illustrating
the timings, it is further assumed that there is only
one device with the matching entry in each block.
Figure 74, page 104 shows the timing diagram for
a SEARCH command in the 272-bit-configured ta-
ble consisting of 31 devices for each of the eight
devices in Block 0. Figure 75, page 105 shows the
timing diagram for a SEARCH command in the
272-bit-configured table of 31 devices for all devic-
es above the winning device in Block 1. Figure 76,
page 106 shows the timing diagram for the global-
ly winning device (the final winner within its own
and all blocks) in Block 1. Figure 77, page 107
shows the timing diagram for all the devices below
the globally winning device in Block 1. Figure 78,
page 108, Figure 79, page 109, and Figure 80,
page 110, respectively, show the timing diagrams
of the devices above the globally winning device,
the globally winning device, and the devices below
the globally winning device for Block 2. Figure 81,
page 111, Figure 82, page 112, Figure 83, page
113, and Figure 84, page 114, respectively, show
the timing diagrams of the device above the glo-
bally winning device, the globally winning device,
the devices below the globally winning device (ex-
cept Device 30), and last device (Device 30) for
Block 3.
# of devices
Max Table Size
Latency in CLK Cycles
1 (TLSZ = 00)
8K x 272-bit
4
2–8 (TLSZ = 01)
64K x 272-bit
5
9–31 (TLSZ = 10)
248K x 272-bit
6
HLAT
Number of CLK Cycles
000
0
001
1
010
2
011
3
100
4
101
5
110
6
111
7
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