- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄359091 > M7020R-083ZA1T (意法半導(dǎo)體) 32K x 68-bit Entry NETWORK SEARCH ENGINE PDF資料下載
參數(shù)資料
| 型號(hào)： | M7020R-083ZA1T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 32K x 68-bit Entry NETWORK SEARCH ENGINE |
| 中文描述： | 32K的× 68位進(jìn)入網(wǎng)絡(luò)搜索引擎 |
| 文件頁(yè)數(shù)： | 62/150頁(yè) |
| 文件大?。?/td> | 996K |
| 代理商： | M7020R-083ZA1T |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)當(dāng)前第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)
M7020R
62/150
Table 31. Latency of SEARCH from Instruction to SRAM Access Cycle, 68-bit, Up to 31 Devices
Table 32. Shift of SSF and SSV from SADR
136-bit Configuration with Single Device
The hardware diagram for this search subsystem
is shown in Figure 41.
Figure 42, page 64 shows the timing diagram for a
SEARCH command in the 136-bit-configured ta-
ble (CFG = 01010101) consisting of a single de-
vice for one set of parameters. This illustration
assumes that the host ASIC has programmed
TLSZ to ’00,’ HLAT to ’001,’ LRAM to ’1,’ and LDEV
to ’1.’
The following is the operation sequence for a sin-
gle 136-bit SEARCH command (refer to COM-
MAND CODES AND PARAMETERS, page 29).
–
Cycle A:
The host ASIC drives the CMDV high
and applies SEARCH command code ('10') to
CMD[1:0] signals. CMD[5:3] signals must be
driven with the index to the GMR pair for use in
this SEARCH operation. CMD[8:7] signals must
be driven with the same bits that will be driven
on SADR[21:20] by this device if it has a hit.
DQ[67:0] must be driven with the 68-bit data
([135:68]) to be compared against all even loca-
tions. The CMD[2] signal must be driven to logic
'0.'
–
Cycle B:
The host ASIC continues to drive the
CMDV high and applies the command code of
SEARCH command ('10') on CMD[1:0].
CMD[5:2] must be driven by the index of the
comparand register pair for storing the 136-bit
word presented on the DQ Bus during Cycles A
and B. CMD[8:6] signals must be driven with the
index of the SSR that will be used for storing the
address of the matching entry and Hit Flag (see
SEARCH-Successful
page 23). The DQ[67:0] is driven with 68-bit
data ([67:0]), compared to all odd locations.
Note:
For 136-bit searches, the host ASIC must
supply two distinct 68-bit data words on
DQ[67:0] during Cycles A and B. The even-
numbered GMR of the pair specified by the
GMR Index is used for masking the word in Cy-
cle A. The odd-numbered GMR of the pair spec-
ified by the GMR Index is used for masking the
word in Cycle B.
Registers
(SSR[0:7]),
# of devices
Max Table Size
Latency in CLK Cycles
1 (TLSZ = 00)
32K x 68-bit
4
2–8 (TLSZ = 01)
256K x 68-bit
5
9–31 (TLSZ = 10)
992K x 68-bit
6
HLAT
Number of CLK Cycles
000
0
001
1
010
2
011
3
100
4
101
5
110
6
111
7
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M7020R | 32K x 68-bit Entry NETWORK SEARCH ENGINE |
| M72DW64000B | 64Mbit (x8/ x16, Multiple Bank, Boot Block) Flash Memory and 16Mbit Pseudo SRAM, 3V Supply, Multiple Memory Product |
| M72DW64000B70ZT | 64Mbit (x8/ x16, Multiple Bank, Boot Block) Flash Memory and 16Mbit Pseudo SRAM, 3V Supply, Multiple Memory Product |
| M72DW64000B90ZT | 64Mbit (x8/ x16, Multiple Bank, Boot Block) Flash Memory and 16Mbit Pseudo SRAM, 3V Supply, Multiple Memory Product |
| M74AC574TTR | OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT NON INVERTING |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M702-230442 | 功能描述:火線接頭 IEEE 1394 SMT 4P HORIZONTAL RoHS:否 制造商:Molex 產(chǎn)品:IEEE 1394 Firewire Connectors 標(biāo)準(zhǔn):IEEE 1394 位置/觸點(diǎn)數(shù)量:6 節(jié)距:2 mm 觸點(diǎn)電鍍:Unplated 觸點(diǎn)材料:Phosphor Bronze 型式:Female 電流額定值:0.5 A 安裝風(fēng)格:Through Hole 端接類型:Solder Tab 連接器類型:Firewire Receptacle |
| M702-230642 | 功能描述:火線接頭 IEEE 1394 SMT 6P HORIZONTAL RoHS:否 制造商:Molex 產(chǎn)品:IEEE 1394 Firewire Connectors 標(biāo)準(zhǔn):IEEE 1394 位置/觸點(diǎn)數(shù)量:6 節(jié)距:2 mm 觸點(diǎn)電鍍:Unplated 觸點(diǎn)材料:Phosphor Bronze 型式:Female 電流額定值:0.5 A 安裝風(fēng)格:Through Hole 端接類型:Solder Tab 連接器類型:Firewire Receptacle |
| M7023 | 制造商:Tamura Corporation of America 功能描述: |
| M7027 | 功能描述:數(shù)字萬(wàn)用表 Dual Display Multime 0.3% Accuracy RoHS:否 制造商:Tektronix 產(chǎn)品:Multimeters 類型:Bench 準(zhǔn)確性:0.04 % 電壓范圍:2 V to 2 kV 電阻范圍: 電容范圍: 顯示計(jì)數(shù): 頻率:10 Hz to 45 Hz, 850 Hz to 1 MHz 測(cè)距: 真均方根值: 數(shù)據(jù)保持: |
| M7029 | 功能描述:數(shù)字萬(wàn)用表 Dual Display Multime 0.2% Accuracy RoHS:否 制造商:Tektronix 產(chǎn)品:Multimeters 類型:Bench 準(zhǔn)確性:0.04 % 電壓范圍:2 V to 2 kV 電阻范圍: 電容范圍: 顯示計(jì)數(shù): 頻率:10 Hz to 45 Hz, 850 Hz to 1 MHz 測(cè)距: 真均方根值: 數(shù)據(jù)保持: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。