參數(shù)資料
型號(hào): M7020R-083ZA1T
廠商: 意法半導(dǎo)體
英文描述: 32K x 68-bit Entry NETWORK SEARCH ENGINE
中文描述: 32K的× 68位進(jìn)入網(wǎng)絡(luò)搜索引擎
文件頁(yè)數(shù): 138/150頁(yè)
文件大?。?/td> 996K
代理商: M7020R-083ZA1T
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M7020R
138/150
SRAM WRITE with a Table of Up to Eight Devices
The following explains the SRAM WRITE opera-
tion done through a table(s) of up to eight devices
with the following parameters (TLSZ = 01). The di-
agram of such a table is shown in Figure 101,
page 139.
The following assumes that SRAM access is done
through M7020R Device 0. Figure 102, page 140
and Figure 103, page 141 show the timing dia-
gram for Device 0 and Device 7, respectively.
Cycle 1A:
The host ASIC applies the WRITE In-
struction on CMD[1:0] using CMDV = 1. The DQ
Bus supplies the address with DQ[20:19] set to
'10' to select the SRAM address. The host ASIC
selects the device for which the ID[4:0] matches
the DQ[25:21] lines. The host ASIC also sup-
plies SADR[23:21] on CMD[8:6] in this cycle.
Note:
CMD[2] must be set to '0' for SRAM
WRITE because Burst WRITEs into the SRAM
are not supported.
Cycle 1B:
The host ASIC continues to apply the
WRITE Instruction on CMD[1:0] using CMDV =
1. The DQ Bus supplies the address with
DQ[20:19] set to '10' to select the SRAM ad-
dress.
Note:
CMD[2] must be set to '0' for SRAM
WRITE because Burst WRITEs into the SRAM
are not supported.
Cycle 2:
The host ASIC continues to drive
DQ[67:0]. The data in this cycle is not used by
the M7020R device.
Cycle 3:
The host ASIC continues to drive
DQ[67:0]. The data in this cycle is not used by
the M7020R device.
At the end of cycle 3, a new command can begin.
The WRITE is a pipelined operation. The WRITE
Cycle appears at the SRAM Bus, however, with
the same latency as that of a SEARCH Instruction,
as measured from the second cycle of the WRITE
command.
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