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參數(shù)資料
| 型號： | M68HC705UGANG |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 英文描述： | High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit |
| 中文描述： | 高密度互補金屬氧化物半導體（HCMOS）微控制器 |
| 文件頁數(shù)： | 87/112頁 |
| 文件大?。?/td> | 809K |
| 代理商： | M68HC705UGANG |
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MC68HC05BD3
10-1
LOW POWER MODES
10
10
LOW POWER MODES
The MC68HC05BD3 has only one low-power operating mode–the Wait Mode. The WAIT
instruction provides the only mode that reduces the power required for the MCU by stopping CPU
internal clock. The STOP instruction is not implemented in its normal sense. The STOP instruction
will be interpreted as the NOP instruction by the CPU if it is ever encountered. The flow of the WAIT
mode is shown in Figure 10-1.
10.1
STOP Mode
Stop mode is not implemented on the MC68HC05BD3. The STOP instruction will be treated and
executed as a NOP instruction. Therefore, the I-bit in the Condition Code register will not be
cleared.
10.2
WAIT Mode
In the WAIT mode the internal processor clock is halted, suspending all processor and internal bus
activities. Other Internal clocks remain active, permitting interrupts to be generated from the
Multi-Function Timer, M-Bus Interface, and the Sync Signal Processor, or a reset to be generated
from the COP watchdog timer. The timer may be used to generate a periodic exit from the WAIT
mode. Execution of the WAIT instruction automatically clears the I-bit in the Condition Code
register, so that any hardware interrupt can wake up the MCU. All other registers, memory, and
input/output lines remain in their previous states.
TPG
85
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
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