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參數(shù)資料
| 型號： | M68HC705UGANG |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit |
| 中文描述： | 高密度互補(bǔ)金屬氧化物半導(dǎo)體（HCMOS）微控制器 |
| 文件頁數(shù)： | 67/112頁 |
| 文件大?。?/td> | 809K |
| 代理商： | M68HC705UGANG |
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MC68HC05BD3
8-7
SYNC SIGNAL PROCESSOR
8
8.3
Registers
There are seven registers associated with the Sync Signal Processor, these are described below.
8.3.1
Sync Signal Control & Status Register (SSCSR)
VPOL - Vertical Sync Input Polarity
1 (set)
–
VSYNC input is positive polarity.
0 (clear) –
VSYNC input is negative polarity.
Vertical Sync Input Polarity flag indicates the polarity of the incoming signal at the VSYNC input.
HPOL - Horizontal Sync Input Polarity
1 (set)
–
HSYNC input is positive polarity.
0 (clear) –
HSYNC input is negative polarity.
Horizontal Sync Input Polarity flag indicates the polarity of the incoming signal at the HSYNC
input.
VDET - Vertical Sync Signal Detect
1 (set)
–
An active vertical sync is detected at VSYNC input.
0 (clear) –
No vertical sync signal at VSYNC input; use internal generated
Vsync for VTTL.
Vertical Sync Signal Detect flag, if set, indicates an active input vertical sync signal has been
detected. If cleared, it indicates there is no active signal, and the VTTL will output the internally
generated Vsync signal. An active vertical sync signal is defined as:
VDET = (VSYNC pulse width < 480
μ
s or 960t
CYC
)·(VSYNC period < 65.5ms or 131x10
3
t
CYC
)
HDET - Horizontal Sync Signal Detect
1 (set)
–
An active horizontal sync is detected at HSYNC input.
0 (clear) –
No horizontal sync signal at HSYNC input; use internal generated
Hsync for HTTL.
Horizontal Sync Signal Detect flag, if set, indicates an active input horizontal sync signal has been
detected. If cleared, it indicates there is no active signal, and the HTTL will output the internally
generated Hsync signal. An active horizontal sync signal is defined as:
HDET=(HSYNC pulse width < 8
μ
s or 16t
CYC
)·(9
μ
s or 18t
CYC
< HSYNC period < 128
μ
s or 256t
CYC
)
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$000C
VPOL
HPOL
VDET
HDET
SOUT
INSRTB
FOUT
VSIN
0000 0000
TPG
65
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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