參數(shù)資料
型號: M68HC705UGANG
廠商: 飛思卡爾半導體(中國)有限公司
英文描述: High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit
中文描述: 高密度互補金屬氧化物半導體(HCMOS)微控制器
文件頁數(shù): 66/112頁
文件大?。?/td> 809K
代理商: M68HC705UGANG
8-6
MC68HC05BD3
SYNC SIGNAL PROCESSOR
8
Figure 8-4
Sync Signal Counters Block Diagram
Figure 8-5
Vertical Frequency Counter Timing
13-bit Vertical Frequency Register
13-bit counter
12-bit counter
12-bit Horizontal Line Count Register
Negative edge detector
VSYNC
HSYNC
System Clock
R
$0D
$0E
$0F
$10
÷
16
Negative edge detector
R
PH2
VSYNIN
Counter signal reset
PH2
÷
16
case1
PH2
÷
16
case2
Counter resets at 4 PH2 cycles
after falling edge of VSYNIN
Counter advances at the
rising edge of the clock
1. The value of the counter will be loaded into the register before it is reset.
2. The Vertical Frequency Counter is clocked by a PH2
÷
16 clock.
3. Because of the asynchronous nature between PH2 and VSYNIN, the register
will have one more count in case 2 than in case 1.
TPG
64
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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