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參數(shù)資料
| 型號： | M68AW127BNK |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 1Mbit 128K x8, 3.0V Asynchronous SRAM |
| 中文描述： | 1Mbit的128K的× 8，3.0V異步SRAM |
| 文件頁數(shù)： | 14/20頁 |
| 文件大?。?/td> | 327K |
| 代理商： | M68AW127BNK |
M68AW127B
14/20
Figure 13. E1 Controlled, Low V
CC
Data Retention AC Waveforms
Note: 1. For 100ns speed class V
DR
≥
2.0V.
Figure 14. E2 Controlled, Low V
CC
Data Retention AC Waveforms
Note: 1. For 100ns speed class V
DR
≥
2.0V.
Table 9. Low V
CC
Data Retention Characteristics
Symbol
Parameter
Note: 1. All other Inputs at V
IH
≥
V
CC
–0.2V or V
IL
≤
0.2V.
2. Tested initially and after any design or process that may affect these parameters.
t
AVAV
is Read cycle time.
3. No input may exceed V
CC
+0.2V.
Test Condition
Min
Typ
Max
4.5
5
Unit
μA
μA
I
CCDR (1)
Supply Current
(Data Retention)
V
CC
= 1.5V, E1
≥
V
CC
–0.2V or
E2
≤
0.2V, f = 0
70
100
t
CDR (1,2)
Chip Deselected to Data
Retention Time
0
ns
t
R (2)
Operation Recovery Time
70
100
70
100
t
AVAV
5
1.5
2.0
ns
ms
V
V
V
DR (1)
Supply Voltage
(Data Retention)
E1
≥
V
CC
–0.2V or
E2
≤
0.2V, f = 0
AI05980
DATA RETENTION MODE
tR
3.6V
tCDR
VCC 2.7V
VDR > 1.5V
(1)
E1
E1
≥
VDR – 0.2V
AI05957B
DATA RETENTION MODE
3.6V
VCC 2.7V
VDR > 1.5V
(1)
E2
≤
0.2V
tCDR
E2
tR
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