參數(shù)資料
型號： M5M4V4265CTP-5S
廠商： Mitsubishi Electric Corporation
英文描述： APUS MFR4200 PBFREE
中文描述： 江戶（超頁）模式4194304位（262144字由16位）動態(tài)隨機存儲器
文件頁數(shù)： 31/31頁
文件大?。?/td> 311K
代理商： M5M4V4265CTP-5S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-5S:under development
All combination of nine row address signals (A
0~
A
8
) are
selected during 512 continuous RAS only refresh cycles
within 8.2 ms.
2. Burst refresh during Read/Write operation
(A) Timing diagram
Read / Write
Self Refresh
Read / Write
t
NSB
t
RASS
≥
100μs
t
SNB
last
refresh cycles
first
refresh cycles
Table 3
Read / Write Cycle
CBR burst
refresh
RAS only
burst refresh
t
NSB
+t
SNB
≤
8.2ms
Definition of CBR burst refresh
The CBR burst refresh performs more than 512 continuous
CBR cycles within 8.2 ms.
Switching from read/write operation to self refresh operation.
The time interval t
NSB
from the falling edge of RAS signal in the
first CBR refresh cycle during read/write operation period to the
falling edge of RAS signal at the start of self refresh operation
should be set within 8.2 ms.
Switching from self refresh operation to read/write operation.
The time interval t
SNB
from the rising edge of RAS signal at the
end of self refresh operation to the falling edge of RAS signal in
the last CBR refresh cycle during read/write operation period
should be set within 8.2 ms.
Switching from read/write operation to self refresh operation.
The time interval from the falling edge of RAS signal in the first
RAS only refresh cycle during read/write operation period
to the falling edge of RAS signal at the start of self refresh
operation should be set within t
NSB
(shown in table 3).
Switching from self refresh operation to read/write operation.
The time interval from the rising edge of RAS signal at the end
of self refresh operation to the falling edge of RAS signal in the
last RAS only refresh cycle during read/write operation period
should be set within t
SNB
(shown in table 3).
RAS
refresh cycles
511 cycles
refresh cycles
511 cycles
(B) Definition of burst refresh
8.2ms
read/write cycles
RAS
refresh cycles
512 cycles
2.2 RAS only burst refresh
2.1 CBR burst refresh
Definition of RAS only burst refresh
31
t
SNB
≤
8.2ms
t
NSB
≤
8.2ms
Read / Write
Self Refresh
Self Refresh
Read / Write
相關(guān)PDF資料
PDF描述
M5M4V4265CTP-6 EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
M5M4V4265CTP-6S EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
M5M4V4265CTP-7 EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
M5M4V4265CTP-7S EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
M5M4V4405CJ EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M5M4V4265CTP-6 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
M5M4V4265CTP-6S 制造商:Mitsubishi Electric 功能描述:256K X 16 EDO DRAM, 60 ns, PDSO40
M5M4V4265CTP-7 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
M5M4V4265CTP-7S 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
M5M4V4405CJ 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
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