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| 型號： | M58LV064A150N1T |
| 廠商： | 意法半導體 |
| 英文描述： | 64 Mbit 4Mb x16 or 2Mb x32, Uniform Block, Burst 3V Supply Flash Memories |
| 中文描述： | 64兆位4Mb的x16或功能的2Mb X32號，統(tǒng)一座，突發(fā)3V電源閃存 |
| 文件頁數(shù)： | 13/65頁 |
| 文件大小： | 450K |
| 代理商： | M58LV064A150N1T |
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M58LV064A, M58LV064B
Clock (K).
The Clock, K, is used to synchronize
the memory with the external bus during Synchro-
nous Bus Read operations. The Clock can be con-
figured to have an active rising or falling edge. Bus
signals are latched on the active edge of the Clock
during synchronous bus operations. In Synchro-
nous Burst Read mode the address is latched on
the first active clock edge when Latch Enable is
low, V
IL
, or on the rising edge of Latch Enable,
whichever occurs first.
During asynchronous bus operations the Clock is
not used.
Burst Address Advance (B).
The Burst Address
Advance, B, controls the advancing of the address
by the internal address counter during synchro-
nous bus operations.
Burst Address Advance, B, is only sampled on the
active clock edge of the Clock when the X- or Y-
latency time has expired. If Burst Address Ad-
vance is Low, V
IL
, the internal address counter ad-
vances. If Burst Address Advance is High, V
IH
, the
internal address counter does not change; the
same data remains on the Data Inputs/Outputs
and Burst Address Advance is not sampled until
the Y-latency expires.
The Burst Address Advance, B, may be tied to V
IL
.
Valid Data Ready (R).
The Valid Data Ready
output, R, is an open drain output that can be used
to identify if the memory is ready to output data or
not. The Valid Data Ready output is only active
during Synchronous Burst Read operations when
the Burst Length is set to Continuous. The Valid
Data Ready output can be configured to be active
on the clock edge of the invalid data read cycle or
one cycle before. Valid Data Ready Low, V
OL
, in-
dicates that the data is not, or will not be valid. Val-
id Data Ready in a high-impedance state indicates
that valid data is or will be available.
If the memory is configured for Synchronous Burst
Read operations with Burst Length set to Continu-
ous then the value of Valid Data Ready, will de-
pend on the starting address. If the starting
address is aligned to a four Word boundary then
the continuous burst mode will run without activat-
ing the Valid Data Ready output. If the starting ad-
dress is not aligned to a four Word boundary, Valid
Data Ready is Low at the beginning of the contin-
uous burst read to indicate that the memory needs
an internal delay to read the content of the four
successive words in the array.
Unless the Burst Length is set to Continuous and
Synchronous Burst Read has been selected, Valid
Data Ready is high-impedance. It may be tied to
other components with the same Valid Data
Ready signal to create a unique System Ready
signal.
When the system clock frequency is between
33MHz and 50MHz and the Y latency is set to 2,
values of B sampled on odd clock cycles, starting
from the first read are not considered.
Designers should use an external pull-up resistor
of the correct value to meet the external timing re-
quirements for Valid Data Ready rising. Refer to
Figure 20.
Word Organization (WORD).
The Word Organi-
zation input, WORD, selects the x16 or x32 Bus
Width on the M58LV064B. The Word Organization
input is not available on the M58LV064A.
When WORD is Low, V
IL
, Word-wide x16 Bus
Width is selected; data is read and written to DQ0-
DQ15; DQ16-DQ31 are at high impedance and A1
is the LSB of the address bus. When WORD is
High, V
IH
, the Double-Word wide x32 Bus Width is
selected and the data is read and written to on
DQ0-DQ31; A2 is the LSB of the address bus and
A1 is don’t care.
Ready/Busy (RB).
The Ready/Busy output, RB,
is an open-drain output that can be used to identify
if the Program/Erase Controller is currently active.
When Ready/Busy is high impedance, the memo-
ry is ready for any Read, Program or Erase opera-
tion. Ready/Busy is Low, V
OL
, during Program and
Erase operations. When the device is busy it will
not accept any additional Program or Erase com-
mands except Program/Erase Suspend. When the
Program/Erase Controller is idle, or suspended,
Ready Busy can float High through a pull-up resis-
tor.
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
Ready/Busy is not Low during a reset unless the
reset was applied when the Program/Erase Con-
troller was active; Ready/Busy can rise before Re-
set/Power-Down rises.
Program/Erase Enable (V
PP
).
The
Erase Enable input, V
PP,
is used to protect all
blocks, preventing Program and Erase operations
from affecting their data.
When Program/Erase Enable is Low, V
IL
, any pro-
gram or erase operation sent to the Command In-
terface will cause the V
PP
Status bit (bit3) in the
Status Register to be set. When Program/Erase
Enable is High, V
IH
, program and erase operations
can be performed on unprotected blocks. Pro-
gram/Erase Enable must be kept High during all
Program, Erase, Block Protect and Block Unpro-
tect operations, otherwise the operation is not
guaranteed to succeed and data may become cor-
rupt.
V
DD
Supply Voltage.
The Supply Voltage, V
DD
,
is the core power supply. All internal circuits draw
Program/
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PDF描述 |
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| M58LV064A150N6T | 64 Mbit 4Mb x16 or 2Mb x32, Uniform Block, Burst 3V Supply Flash Memories |
| M58LV064A150ZA6T | 64 Mbit 4Mb x16 or 2Mb x32, Uniform Block, Burst 3V Supply Flash Memories |
| M58LW032C | 32 Mbit 2Mb x16, Uniform Block, Burst 3V Supply Flash Memory |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M58LV064A150N6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit 4Mb x16 or 2Mb x32, Uniform Block, Burst 3V Supply Flash Memories |
| M58LV064A150ZA1 | 功能描述:閃存 4Mx16 or 2Mx32 150ns RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| M58LV064A150ZA1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit 4Mb x16 or 2Mb x32, Uniform Block, Burst 3V Supply Flash Memories |
| M58LV064A150ZA6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit 4Mb x16 or 2Mb x32, Uniform Block, Burst 3V Supply Flash Memories |
| M58LV064B | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit 4Mb x16 or 2Mb x32, Uniform Block, Burst 3V Supply Flash Memories |
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