參數(shù)資料
型號(hào): M58LT128GST
廠商: 意法半導(dǎo)體
英文描述: 128Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Secure Flash Memories
中文描述: 128Mbit(8兆x16插槽,多銀行,多層次,多突發(fā))1.8V電源安全閃存
文件頁(yè)數(shù): 79/98頁(yè)
文件大?。?/td> 693K
代理商: M58LT128GST
M58LT128GST, M58LT128GSB
13 Part Numbering
79/98
Table 44.
Bank and Erase Block Region 1 Information
Flash memory (top)
Flash memory
(bottom)
Description
Offset
Data
Offset
Data
(P+24)h = 12Eh
0Fh
(P+24)h = 12Eh
01h
Number of identical banks within Bank Region 1
(P+25)h = 12Fh
00h
(P+25)h = 12Fh
00h
(P+26)h = 130h
11h
(P+26)h = 130h
11h
Number of program or erase operations allowed in Bank
Region 1:
Bits 0-3: Number of simultaneous program operations
Bits 4-7: Number of simultaneous erase operations
(P+27)h = 131h
00h
(P+27)h = 131h
00h
Number of program or erase operations allowed in other
banks while a bank in same region is programming
Bits 0-3: Number of simultaneous program operations
Bits 4-7: Number of simultaneous erase operations
(P+28)h = 132h
00h
(P+28)h = 132h
00h
Number of program or erase operations allowed in other
banks while a bank in this region is erasing
Bits 0-3: Number of simultaneous program operations
Bits 4-7: Number of simultaneous erase operations
(P+29)h = 133h
01h
(P+29)h = 133h
02h
Types of erase block regions in Bank Region 1
n = number of erase block regions with contiguous same-size
erase blocks.
Symmetrically blocked banks have one blocking region
(2)
.
(P+2A)h = 134h
07h
(P+2A)h = 134h
03h
Bank Region 1 Erase Block Type 1 Information
Bits 0-15: n+1 = number of identical-sized erase blocks
Bits 16-31: n×256 = number of bytes in erase block region
(P+2B)h = 135h
00h
(P+2B)h = 135h
00h
(P+2C)h = 136h
00h
(P+2C)h = 136h
80h
(P+2D)h = 137h
02h
(P+2D)h = 137h
00h
(P+2E)h = 138h
64h
(P+2E)h = 138h
64h
Bank Region 1 (Erase Block Type 1)
Minimum block erase cycles × 1000
(P+2F)h = 139h
00h
(P+2F)h = 139h
00h
(P+30)h = 13Ah
02h
(P+30)h = 13Ah
02h
Bank Region 1 (Erase Block Type 1): BIts per cell, internal
ECC
Bits 0-3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
BIts 5-7: reserved
(P+31)h = 13Bh
03h
(P+31)h = 13Bh
03h
Bank Region 1 (Erase Block Type 1): Page mode and
Synchronous mode capabilities
Bit 0: Page-mode reads permitted
Bit 1: Synchronous reads permitted
Bit 2: Synchronous writes permitted
Bits 3-7: reserved
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