參數(shù)資料
型號(hào): M58LT128GST1ZA5F
廠商: 意法半導(dǎo)體
英文描述: 128Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Secure Flash Memories
中文描述: 128Mbit(8兆x16插槽,多銀行,多層次,多突發(fā))1.8V電源安全閃存
文件頁(yè)數(shù): 44/98頁(yè)
文件大?。?/td> 693K
代理商: M58LT128GST1ZA5F
7 Read modes
M58LT128GST, M58LT128GSB
44/98
WAIT being gated by E, it will remain active and will not revert to high impedance when G goes
High. So if two or more devices are connected to the system’s READY signal, to prevent bus
contention the WAIT signal of the M58LT128GST and M58LT128GSB should not be directly
connected to the system’s READY signal.
WAIT will revert to high-impedance when Output Enable, G, or Chip Enable, E, goes High.
See
Table 23: Synchronous Read AC Characteristics
, and
Figure 13: Synchronous Burst Read
Suspend AC Waveforms
, for details.
7.2.2
Single Synchronous Read mode
Single Synchronous Read operations are similar to Synchronous Burst Read operations except
that the memory outputs the same data to the end of the operation.
Synchronous Single Reads are used to read the Electronic Signature, Status Register, CFI,
Configuration Register Status, or Protection Register. When the addressed bank is in Read
CFI, Read Status Register or Read Electronic Signature mode, the WAIT signal is deasserted
when Output Enable, G, is at V
IH
or for the one clock cycle during which output data is valid.
Otherwise, it is asserted.
See
Table 23: Synchronous Read AC Characteristics
, and
Figure 11: Synchronous Burst Read
AC Waveforms
, for details.
相關(guān)PDF資料
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