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參數資料
| 型號： | M58LT128GST1ZA5F |
| 廠商： | 意法半導體 |
| 英文描述： | 128Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Secure Flash Memories |
| 中文描述： | 128Mbit（8兆x16插槽，多銀行，多層次，多突發(fā)）1.8V電源安全閃存 |
| 文件頁數： | 13/98頁 |
| 文件大小： | 693K |
| 代理商： | M58LT128GST1ZA5F |
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M58LT128GST, M58LT128GSB
2 Signal descriptions
13/98
2
Signal descriptions
See
Figure 1: Logic Diagram
and
Table 1: Signal Names
, for a brief overview of the signals
connected to this device.
2.1
Address Inputs (A0-A22)
The Address Inputs select the cells in the memory array to access during Bus Read operations.
During Bus Write operations they control the commands sent to the Command Interface of the
Program/Erase Controller.
2.2
Data Input/Output (DQ0-DQ15)
The Data I/O output the data stored at the selected address during a Bus Read operation or
input a command or the data to be programmed during a Bus Write operation.
2.3
Chip Enable (E)
The Chip Enable input activates the memory control logic, input buffers, decoders and sense
amplifiers. When Chip Enable is at V
IL
and
Reset is at V
IH
the device is in active mode. When
Chip Enable is at V
IH
the memory is deselected, the outputs are high impedance and the power
consumption is reduced to the stand-by level.
2.4
Output Enable (G)
The Output Enable input controls data outputs during the Bus Read operation of the memory.
2.5
Write Enable (W)
The Write Enable input controls the Bus Write operation of the memory’s Command Interface.
The data and address inputs are latched on the rising edge of Chip Enable or Write Enable
whichever occurs first.
2.6
Reset (RP)
The Reset input provides a hardware reset of the memory. When Reset is at V
IL
, the memory is
in reset mode: the outputs are high impedance and the current consumption is reduced to the
Reset Supply Current I
DD2
. Refer to
Table 20: DC Characteristics - Currents
, for the value of
I
DD2.
After Reset all blocks are in the Protected state and the Configuration Register is reset.
When Reset is at V
IH
, the device is in normal operation. Exiting reset mode the device enters
asynchronous read mode, but a negative transition of Chip Enable or Latch Enable is required
to ensure valid data outputs.
The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied to
V
RPH
(refer to
Table 21: DC Characteristics - Voltages
).
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相關代理商/技術參數 |
參數描述 |
|---|---|
| M58LT128HSB | 制造商:NUMONYX 制造商全稱:Numonyx B.V 功能描述:128 Mbit (8 Mb 】16, multiple bank, multilevel interface, burst) 1.8 V supply, secure Flash memories |
| M58LT128HSB8ZA6 | 制造商:Micron Technology Inc 功能描述:NOR Flash Parallel/Serial 1.8V 128Mbit 8M x 16bit 85ns 64-Pin TBGA Tray 制造商:Micron Technology Inc 功能描述:STD FLASH - Trays |
| M58LT128HSB8ZA6E | 功能描述:IC FLASH 128MBIT 85NS 64TBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:3,000 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:32K (4K x 8) 速度:100kHz，400kHz 接口:I²C，2 線串口 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 125°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:8-SOIC 包裝:帶卷 (TR) 其它名稱:CAV24C32WE-GT3OSTR |
| M58LT128HSB8ZA6F | 功能描述:IC FLASH 128MBIT 85NS 64TBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:2,500 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:1K (128 x 8) 速度:100kHz 接口:UNI/O?（單線） 電源電壓:1.8 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應商設備封裝:8-MSOP 包裝:帶卷 (TR) |
| M58LT128HSB8ZA6T | 制造商:NUMONYX 制造商全稱:Numonyx B.V 功能描述:128 Mbit (8 Mb 】16, multiple bank, multilevel interface, burst) 1.8 V supply, secure Flash memories |
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