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參數(shù)資料
| 型號(hào)： | M58LT128GST1ZA5 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 128Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Secure Flash Memories |
| 中文描述： | 128Mbit（8兆x16插槽，多銀行，多層次，多突發(fā)）1.8V電源安全閃存 |
| 文件頁(yè)數(shù)： | 35/98頁(yè) |
| 文件大?。?/td> | 693K |
| 代理商： | M58LT128GST1ZA5 |
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M58LT128GST, M58LT128GSB
6 Configuration Register
35/98
6
Configuration Register
The Configuration Register is used to configure the type of bus access that the memory will
perform. Refer to Read Modes section for details on read operations.
The Configuration Register is set through the Command Interface using the Set Configuration
Register command. After a reset or power-up the device is configured for asynchronous read
(CR15 = 1). The Configuration Register bits are described in
Table 10
They specify the
selection of the burst length, burst type, burst X latency and the read operation. Refer to
Figure 5
and
Figure 6
for examples of synchronous burst configurations.
6.1
Read Select Bit (CR15)
The Read Select bit, CR15, is used to switch between Asynchronous and Synchronous Read
operations.
When the Read Select bit is set to ’1’, read operations are asynchronous; when the Read
Select bit is set to ’0’, read operations are synchronous.
Synchronous Burst Read is supported in both parameter and main blocks and can be
performed across banks.
On reset or power-up the Read Select bit is set to ’1’ for asynchronous access.
6.2
X-Latency Bits (CR13-CR11)
The X-Latency bits are used during Synchronous Read operations to set the number of clock
cycles between the address being latched and the first data becoming available. For correct
operation the X-Latency bits can only assume the values in
Table 10: Configuration Register
.
The correspondence between X-Latency settings and the maximum sustainable frequency
must be calculated taking into account some system parameters. Two conditions must be
satisfied:
1.
Depending on whether t
AVK_CPU
or t
DELAY
is supplied either one of the following two
equations must be satisfied:
(n + 1) t
K
≥
t
AVQV
- t
AVK_CPU
+ t
QVK_CPU
(n + 2) t
K
≥
t
AVQV
+ t
DELAY
+ t
QVK_CPU
2.
and also
t
K
> t
KQV
+ t
QVK_CPU
where
●
n is the chosen X-Latency configuration code
t
K
is the clock period
t
AVK_CPU
is clock to address valid, L Low, or E Low, whichever occurs last
t
DELAY
is address valid, L Low, or E Low to clock, whichever occurs last
t
QVK_CPU
is the data setup time required by the system CPU,
t
KQV
is the clock to data valid time
t
AVQV
is the random access time of the device.
●
●
●
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相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M58LT128GSB | 128Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Secure Flash Memories |
| M58LT128GSB1ZA5 | 128Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Secure Flash Memories |
| M58LT128GS | 128Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Secure Flash Memories |
| M58LT128GST1ZA5E | 128Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Secure Flash Memories |
| M58LT128GST1ZA5F | 128Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Secure Flash Memories |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M58LT128GST1ZA5E | 制造商:STMicroelectronics 功能描述: |
| M58LT128GST1ZA5F | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Secure Flash Memories |
| M58LT128HSB | 制造商:NUMONYX 制造商全稱:Numonyx B.V 功能描述:128 Mbit (8 Mb 】16, multiple bank, multilevel interface, burst) 1.8 V supply, secure Flash memories |
| M58LT128HSB8ZA6 | 制造商:Micron Technology Inc 功能描述:NOR Flash Parallel/Serial 1.8V 128Mbit 8M x 16bit 85ns 64-Pin TBGA Tray 制造商:Micron Technology Inc 功能描述:STD FLASH - Trays |
| M58LT128HSB8ZA6E | 功能描述:IC FLASH 128MBIT 85NS 64TBGA RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:32K (4K x 8) 速度:100kHz，400kHz 接口:I²C，2 線串口 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 125°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOIC 包裝:帶卷 (TR) 其它名稱:CAV24C32WE-GT3OSTR |
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