參數(shù)資料
型號(hào)： M58LT128GSB1ZA5E
廠商： 意法半導(dǎo)體
英文描述： 128Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Secure Flash Memories
中文描述： 128Mbit（8兆x16插槽，多銀行，多層次，多突發(fā)）1.8V電源安全閃存
文件頁(yè)數(shù)： 20/98頁(yè)
文件大?。?/td> 693K
代理商： M58LT128GSB1ZA5E
4 Command Interface
M58LT128GST, M58LT128GSB
20/98
cycles will output the Electronic Signature data and the Program/Erase controller will continue
to program or erase in the background.
The Read Electronic Signature command will only change the read mode of the addressed
bank. The read modes of other banks are not affected. Only Asynchronous Read and Single
Synchronous Read operations should be used to read the Electronic Signature. A Read Array
command is required to return the bank to Read Array mode.
4.4
Read CFI Query command
The Read CFI Query command is used to read data from the Common Flash Interface (CFI).
One Bus Write cycle is required to issue the Read CFI Query command. Once a bank is in
Read CFI Query mode, subsequent Bus Read operations in the same bank read from the
Common Flash Interface.
The Read CFI Query command can be issued at any time, even during program or erase
operations.
If a Read CFI Query command is issued to a bank that is executing a program or erase
operation the bank will go into Read CFI Query mode. Subsequent Bus Read cycles will output
the CFI data and the Program/Erase controller will continue to program or erase in the
background.
The Read CFI Query command will only change the read mode of the addressed bank. The
read modes of other banks are not affected. Only Asynchronous Read and Single Synchronous
Read operations should be used to read from the CFI. A Read Array command is required to
return the bank to Read Array mode. Dual operations between the Parameter Bank and the CFI
memory space are not allowed (see
Table 15: Dual Operation Limitations
for details).
See
Appendix B: Common Flash Interface
,
Table 36
,
Table 37
,
Table 38
,
Table 39
,
Table 40
,
Table 42
,
Table 43
,
Table 44
and
Table 45
for details on the information contained in the
Common Flash Interface memory area.
4.5
Clear Status Register command
The Clear Status Register command can be used to reset (set to ‘0’) all error bits (SR1, 3, 4
and 5) in the Status Register.
One Bus Write cycle is required to issue the Clear Status Register command. The Clear Status
Register command does not affect the read mode of the bank.
The error bits in the Status Register do not automatically return to ‘0’ when a new command is
issued. The error bits in the Status Register should be cleared before attempting a new
program or erase command.
相關(guān)PDF資料
PDF描述
M58LT128GSB1ZA5F 128Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Secure Flash Memories
M58LT128GST1ZA5 128Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Secure Flash Memories
M58LT128GSB 128Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Secure Flash Memories
M58LT128GSB1ZA5 128Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Secure Flash Memories
M58LT128GS 128Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Secure Flash Memories
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M58LT128GSB1ZA5F 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Secure Flash Memories
M58LT128GST 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Secure Flash Memories
M58LT128GST1ZA5 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Secure Flash Memories
M58LT128GST1ZA5E 制造商:STMicroelectronics 功能描述:
M58LT128GST1ZA5F 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Secure Flash Memories
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