參數(shù)資料
型號： M58LT128GSB1ZA5
廠商： 意法半導(dǎo)體
英文描述： 128Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Secure Flash Memories
中文描述： 128Mbit（8兆x16插槽，多銀行，多層次，多突發(fā)）1.8V電源安全閃存
文件頁數(shù)： 37/98頁
文件大?。?/td> 693K
代理商： M58LT128GSB1ZA5
M58LT128GST, M58LT128GSB
6 Configuration Register
37/98
6.7
Valid Clock Edge Bit (CR6)
The Valid Clock Edge bit, CR6, is used to configure the active edge of the Clock, K, during
synchronous read operations. When the Valid Clock Edge bit is Low (set to ’0’) the falling edge
of the Clock is the active edge. When the Valid Clock Edge bit is High (set to ’1’) the rising edge
of the Clock is the active edge.
6.8
Wrap Burst Bit (CR3)
The Wrap Burst bit, CR3, is used to select between wrap and no wrap. Synchronous burst
reads can be confined inside the 4, 8 or 16 Word boundary (wrap) or overcome the boundary
(no wrap).
When the Wrap Burst bit is Low (set to ‘0’) the burst read wraps. When it is High (set to ‘1’) the
burst read does not wrap.
6.9
Burst length Bits (CR2-CR0)
The Burst Length bits are used to set the number of Words to be output during a Synchronous
Burst Read operation as result of a single address latch cycle.
They can be set for 4 Words, 8 Words, 16 Words or continuous burst, where all the Words are
read sequentially. In continuous burst mode the burst sequence can cross bank boundaries.
In continuous burst mode, in 4, 8 or 16 Words no-wrap, depending on the starting address, the
device asserts the WAIT signal to indicate that a delay is necessary before the data is output.
If the starting address is aligned to an 8 Word boundary no WAIT states are needed and the
WAIT output is not asserted.
If the starting address is not aligned to the 8 Word boundary, WAIT will be asserted when the
burst sequence crosses the first 16 Word boundary to indicate that the device needs an internal
delay to read the successive Words in the array.
In the worst case, the number of WAIT states is one clock cycle less than the latency setting.
The exact number is reported in
Table 12: Wait at the Boundary
.
WAIT will be asserted only once during a continuous burst access. See also
Table 11: Burst
Type Definition
.
CR14, CR5
and
CR4
are reserved for future use.
相關(guān)PDF資料
PDF描述
M58LT128GS 128Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Secure Flash Memories
M58LT128GST1ZA5E 128Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Secure Flash Memories
M58LT128GST1ZA5F 128Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Secure Flash Memories
M58LT128GST 128Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Secure Flash Memories
M58LV064A150ZA1T 64 Mbit 4Mb x16 or 2Mb x32, Uniform Block, Burst 3V Supply Flash Memories
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M58LT128GSB1ZA5E 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Secure Flash Memories
M58LT128GSB1ZA5F 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Secure Flash Memories
M58LT128GST 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Secure Flash Memories
M58LT128GST1ZA5 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Secure Flash Memories
M58LT128GST1ZA5E 制造商:STMicroelectronics 功能描述:
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