參數(shù)資料
型號： M58LT128GS
廠商： 意法半導(dǎo)體
英文描述： 128Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Secure Flash Memories
中文描述： 128Mbit（8兆x16插槽，多銀行，多層次，多突發(fā)）1.8V電源安全閃存
文件頁數(shù)： 36/98頁
文件大?。?/td> 693K
代理商： M58LT128GS
6 Configuration Register
M58LT128GST, M58LT128GSB
36/98
Refer to
Figure 5: X-Latency and Data Output Configuration Example
.
6.3
Wait Polarity Bit (CR10)
The Wait Polarity bit is used to set the polarity of the Wait signal used in Synchronous Burst
Read mode. During Synchronous Burst Read mode the Wait signal indicates whether the data
output are valid or a WAIT state must be inserted.
When the Wait Polarity bit is set to ‘0’ the Wait signal is active Low. When the Wait Polarity bit is
set to ‘1’ the Wait signal is active High.
6.4
Data Output Configuration Bit (CR9)
The Data Output Configuration bit is used to configure the output to remain valid for either one
or two clock cycles during synchronous mode.
When the Data Output Configuration Bit is ’0’ the output data is valid for one clock cycle, when
the Data Output Configuration Bit is ’1’ the output data is valid for two clock cycles.
The Data Output Configuration must be configured using the following condition:
t
K
> t
KQV
+ t
QVK_CPU
●
where
●
t
K
is the clock period
t
QVK_CPU
is the data setup time required by the system CPU
t
KQV
is the clock to data valid time.
●
●
If this condition is not satisfied, the Data Output Configuration bit should be set to ‘1’ (two clock
cycles). Refer to
Figure 5: X-Latency and Data Output Configuration Example
.
6.5
Wait Configuration Bit (CR8)
The Wait Configuration bit is used to control the timing of the Wait output pin, WAIT, in
Synchronous Burst Read mode.
When WAIT is asserted, Data is Not Valid and when WAIT is deasserted, Data is Valid.
When the Wait Configuration bit is Low (set to ’0’) the Wait output pin is asserted during the
WAIT state. When the Wait Configuration bit is High (set to ’1’), the Wait output pin is asserted
one data cycle before the WAIT state.
6.6
Burst Type Bit (CR7)
The Burst Type bit determines the sequence of addresses read during Synchronous Burst
Reads.
The Burst Type bit is High (set to ’1’), as the memory outputs from sequential addresses only.
See
Table 11: Burst Type Definition
, for the sequence of addresses output from a given starting
address in sequential mode.
相關(guān)PDF資料
PDF描述
M58LT128GST1ZA5E 128Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Secure Flash Memories
M58LT128GST1ZA5F 128Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Secure Flash Memories
M58LT128GST 128Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Secure Flash Memories
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M58LT128GSB 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Secure Flash Memories
M58LT128GSB1ZA5 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Secure Flash Memories
M58LT128GSB1ZA5E 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Secure Flash Memories
M58LT128GSB1ZA5F 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Secure Flash Memories
M58LT128GST 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Secure Flash Memories
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