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參數(shù)資料
| 型號(hào)： | M58CR064Q90ZB6T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 64 Mbit 4Mb x 16, Dual Bank, Burst 1.8V Supply Flash Memory |
| 中文描述： | 64兆位4Mb的× 16，雙行，突發(fā)1.8V電源快閃記憶體 |
| 文件頁(yè)數(shù)： | 10/70頁(yè) |
| 文件大小： | 1000K |
| 代理商： | M58CR064Q90ZB6T |
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
10/70
SIGNAL DESCRIPTIONS
See Figure 2 Logic Diagram and Table 1,Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A21).
The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the internal state machine.
Data Input/Output (DQ0-DQ15).
The Data I/O
outputs the data stored at the selected address
during a Bus Read operation or inputs a command
or the data to be programmed during a Bus Write
operation.
Chip Enable (E).
The Chip Enable input acti-
vates the memory control logic, input buffers, de-
coders and sense amplifiers. When Chip Enable is
at V
IL
and
Reset/Power-Down is at V
IH
the device
is in active mode. When Chip Enable is at V
IH
the
memory is deselected, the outputs are high imped-
ance and the power consumption is reduced to the
stand-by level.
Output Enable (G).
The Output Enable controls
the outputs during the Bus Read operation of the
memory.
Write Enable (W).
The Write Enable controls the
Bus Write operation of the memory’s Command
Interface. The data and address inputs are latched
on the rising edge of Chip Enable or Write Enable
whichever occurs first.
Write Protect (WP).
Write Protect is an input
that gives an additional hardware protection for
each block. When Write Protect is at V
IL
, the Lock-
Down is enabled and the protection status of the
Locked-Down blocks cannot be changed. When
Write Protect is at V
IH
, the Lock-Down is disabled
and the Locked-Down blocks can be locked or un-
locked. (refer to Table 13, Lock Status).
Reset/Power-Down (RP).
The
Down input provides a hardware reset of the mem-
ory, and/or Power-Down functions, depending on
the Configuration Register status. When Reset/
Power-Down is at V
IL
, the memory is in reset
mode: the outputs are high impedance and if the
Power-Down function is enabled the current con-
sumption is reduced to the Reset Supply Current
I
DD2
. Refer to Table 18, DC Characteristics - Cur-
rents for the value of I
DD2.
After Reset all blocks
are in the Locked state and the Configuration Reg-
ister is reset. When Reset/Power-Down is at V
IH
,
the device is in normal operation. Exiting reset
mode the device enters asynchronous read mode,
but a negative transition of Chip Enable or Latch
Enable is required to ensure valid data outputs.
The Reset/Power-Down pin can be interfaced with
3V logic without any additional circuitry. It can be
Reset/Power-
tied to V
RPH
(refer to Table 19, DC Characteris-
tics).
Latch Enable (L).
Latch Enable latches the ad-
dress bits on its rising edge. The address latch is
transparent when Latch Enable is at V
IL
and it is in-
hibited when Latch Enable is at V
IH
. Latch Enable
can be kept Low (also at board level) when the
Latch Enable function is not required or supported.
Clock (K).
The clock input synchronizes the
memory to the microcontroller during synchronous
read operations; the address is latched on a Clock
edge (rising or falling, according to the configura-
tion settings) when Latch Enable is at V
IL
. Clock is
don't care during asynchronous read and in write
operations.
Wait (WAIT).
Wait is an output signal used during
synchronous read to indicate whether the data on
the output bus are valid. This output is high imped-
ance when Chip Enable or Output Enable are at
V
IH
or Reset/Power-Down is at V
IL
. It can be con-
figured to be active during the wait cycle or one
clock cycle in advance.
V
DD
Supply Voltage.
V
DD
provides the power
supply to the internal core of the memory device.
It is the main power supply for all operations
(Read, Program and Erase).
V
DDQ
Supply Voltage.
V
DDQ
provides the power
supply to the I/O pins and enables all Outputs to
be powered independently from V
DD
. V
DDQ
can be
tied to V
DD
or can use a separate supply.
V
PP
Program Supply Voltage.
V
PP
is both a
control input and a power supply pin. In
M58CR064C/D the two functions are selected by
the voltage range applied to the pin. In the
M58CR064P/Q the control feature is disabled.
In M58CR064C/D if V
PP
is kept in a low voltage
range (0V to V
DDQ
) V
PP
is seen as a control input.
In this case a voltage lower than V
PPLK
gives an
absolute protection against program or erase,
while V
PP
> V
PP1
enables these functions (see Ta-
bles 18 and 19, DC Characteristics for the relevant
values). V
PP
is only sampled at the beginning of a
program or erase; a change in its value after the
operation has started does not have any effect and
program or erase operations continue.
If V
PP
is in the range of V
PPH
it acts as a power
supply pin. In this condition V
PP
must be stable un-
til the Program/Erase algorithm is completed.
V
SS
Ground.
V
SS
ground is the reference for the
core supply. It must be connected to the system
ground.
V
SSQ
Ground.
V
SSQ
ground is the reference for
the input/output circuitry driven by V
DDQ
. V
SSQ
must be connected to V
SS
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M58CR064QZB | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit 4Mb x 16, Dual Bank, Burst 1.8V Supply Flash Memory |
| M58CR064-ZBT | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit 4Mb x 16, Dual Bank, Burst 1.8V Supply Flash Memory |
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| M5-8L | 制造商:SPC Multicomp 功能描述:IC PAD |
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