參數(shù)資料
型號(hào): M58CR064P12ZB6T
廠商: 意法半導(dǎo)體
英文描述: 64 Mbit 4Mb x 16, Dual Bank, Burst 1.8V Supply Flash Memory
中文描述: 64兆位4Mb的× 16,雙行,突發(fā)1.8V電源快閃記憶體
文件頁(yè)數(shù): 57/70頁(yè)
文件大?。?/td> 1000K
代理商: M58CR064P12ZB6T
57/70
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Table 35. Burst Read Information
(P+D)h = 46h
00C0h
V
PP
Supply Optimum Program/Erase voltage
bit 7 to 4HEX value in volts
bit 3 to 0BCD value in 100 mV
12V
(P+E)h = 47h
(P+F)h = 48h
(P+10)h = 49h
(P+11)h = 4Ah
(P+12)h = 4Bh
0000h
Reserved
Offset
Data
Description
Value
(P+13)h = 4Ch
0003h
Page-mode read capability
bits 0-7
’n’ such that 2
n
HEX value represents the number of read-
page bytes. See offset 28h for device word width to
determine page-mode data output width.
8 Bytes
(P+14)h = 4Dh
0003h
Number of synchronous mode read configuration fields that follow.
3
(P+15)h = 4Eh
0001h
Synchronous mode read capability configuration 1
bit 3-7
Reserved
bit 0-2
’n’ such that 2
n+1
HEX value represents the maximum
number of continuous synchronous reads when the device is
configured for its maximum word width. A value of 07h
indicates that the device is capable of continuous linear bursts
that will output data until the internal burst counter reaches
the end of the device’s burstable address space. This field’s
3-bit value can be written directly to the read configuration
register bit 0-2 if the device is configured for its maximum
word width. See offset 28h for word width to determine the
burst data output width.
4
(P+16)h = 4Fh
0002h
Synchronous mode read capability configuration 2
8
(P+17)h = 50h
0007h
Synchronous mode read capability configuration 3
Cont.
(P+18)h = 51h
0036h
Max operating clock frequency (MHz)
54 MHz
(P+19)h = 52h
0001h
Supported handshaking signal (WAIT pin)
bit 0 during synchronous read (1 = Yes, 0 = No)
bit 1 during asynchronous read (1 = Yes, 0 = No)
Yes
No
Offset
Data
Description
Value
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