參數(shù)資料
型號(hào)： M58CR064CZB
廠商： 意法半導(dǎo)體
英文描述： 64 Mbit 4Mb x 16, Dual Bank, Burst 1.8V Supply Flash Memory
中文描述： 64兆位4Mb的× 16，雙行，突發(fā)1.8V電源快閃記憶體
文件頁(yè)數(shù)： 6/70頁(yè)
文件大?。?/td> 1000K
代理商： M58CR064CZB
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
6/70
SUMMARY DESCRIPTION
The M58CR064 is a 64 Mbit (4Mbit x16) non-vola-
tile Flash memory that may be erased electrically
at block level and programmed in-system on a
Word-by-Word basis using a 1.65V to 2V V
DD
sup-
ply for the circuitry and a 1.65V to 3.3V V
DDQ
sup-
ply for the Input/Output pins. An optional 12V V
PP
power supply is provided to speed up customer
programming. In M58CR064C and M58CR064D
the V
PP
pin can also be used as a control pin to
provide absolute protection against program or
erase. In M58CR064P and M58CR064Q this fea-
ture is disabled.
The device features an asymmetrical block archi-
tecture. M58CR064 has an array of 135 blocks,
and is divided into two banks, Banks A and B. The
Dual Bank Architecture allows Dual Operations,
while programming or erasing in one bank, Read
operations are possible in the other bank. Only
one bank at a time is allowed to be in Program or
Erase mode. It is possible to perform burst reads
that cross bank boundaries. The bank architecture
is summarized in Table 2, and the memory maps
are shown in Figure 4. The Parameter Blocks are
located at the top of the memory address space for
the M58CR064C and M58CR064P, and at the bot-
tom for the M58CR064D and M58CR064Q.
Each block can be erased separately. Erase can
be suspended, in order to perform program in any
other block, and then resumed. Program can be
suspended to read data in any other block and
then resumed. Each block can be programmed
and erased over 100,000 cycles using the supply
voltage V
DD
.
Program and Erase commands are written to the
Command Interface of the memory. An internal
Program/Erase Controller takes care of the tim-
ings necessary for program and erase operations.
The end of a program or erase operation can be
detected and any error conditions identified in the
Status Register. The command set required to
control the memory is consistent with JEDEC stan-
dards.
The device supports synchronous burst read and
asynchronous read from all blocks of the memory
array; at power-up the device is configured for
asynchronous read. In synchronous burst mode,
data is output on each clock cycle at frequencies
of up to 54MHz.
The M58CR064 features an instant, individual
block locking scheme that allows any block to be
locked or unlocked with no latency, enabling in-
stant code and data protection. All blocks have
three levels of protection. They can be locked and
locked-down individually preventing any acciden-
tal programming or erasure. In M58CR064C and
M58CR064D there is an additional hardware pro-
tection against program and erase. When V
PP
≤
V
PPLK
all blocks are protected against program or
erase. All blocks are locked at Power- Up.
The device includes a Protection Register and a
Security Block to increase the protection of a sys-
tem’s design. The Protection Register is divided
into two segments: a 64 bit segment containing a
unique device number written by ST, and a 128 bit
segment One-Time-Programmable (OTP) by the
user. The user programmable segment can be
permanently protected. The Security Block, pa-
rameter block 0, can be permanently protected by
the user. Figure 5, shows the Security Block and
Protection Register Memory Map.
The memory is offered in a TFBGA56, 6.5 x
10mm, 0.75 mm ball pitch package and is supplied
with all the bits erased (set to ’1’).
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