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參數(shù)資料
| 型號： | M58CR064C12ZB6T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 64 Mbit 4Mb x 16, Dual Bank, Burst 1.8V Supply Flash Memory |
| 中文描述： | 64兆位4Mb的× 16，雙行，突發(fā)1.8V電源快閃記憶體 |
| 文件頁數(shù)： | 11/70頁 |
| 文件大?。?/td> | 1000K |
| 代理商： | M58CR064C12ZB6T |
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11/70
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Note: Each device in a system should have
V
DD
,
V
DDQ
and V
PP
decoupled with a 0.1μF ce-
ramic capacitor close to the pin (high frequen-
cy, inherently low inductance capacitors
should be as close as possible to the pack-
age). See Figure 9, AC Measurement Load Cir-
cuit. The PCB track widths should be sufficient
to carry the required V
PP
program and erase
currents.
BUS OPERATIONS
There are six standard bus operations that control
the device. These are Bus Read, Bus Write, Ad-
dress Latch, Output Disable, Standby and Reset.
See Table 3, Bus Operations, for a summary.
Typically glitches of less than 5ns on Chip Enable
or Write Enable are ignored by the memory and do
not affect Bus Write operations.
Bus Read.
Bus Read operations are used to out-
put the contents of the Memory Array, the Elec-
tronic Signature, the Status Register and the
Common Flash Interface. Both Chip Enable and
Output Enable must be at V
IL
in order to perform a
read operation. The Chip Enable input should be
used to enable the device. Output Enable should
be used to gate data onto the output. The data
read depends on the previous command written to
the memory (see Command Interface section).
Refer to the Read AC Waveform figures and Char-
acteristics tables in the DC and AC Parameters
section for details of when the output becomes val-
id.
Bus Write.
Bus Write operations write Com-
mands to the memory or latch Input Data to be
programmed. A bus write operation is initiated
when Chip Enable and Write Enable are at V
IL
with
Output Enable at V
IH
. Commands, Input Data and
Addresses are latched on the rising edge of Write
Enable or Chip Enable, whichever occurs first. The
addresses can also be latched prior to the write
operation by toggling Latch Enable. In this case
the Latch Enable should be tied to V
IH
during the
bus write operation.
See Figures 14 and 15, Write AC Waveforms, and
Tables 22 and 23, Write AC Characteristics, for
details of the timing requirements.
Address Latch.
Address latch operations input
valid addresses. Both Chip enable and Latch En-
able must be at V
IL
during address latch opera-
tions. The addresses are latched on the rising
edge of Latch Enable.
Output Disable.
The outputs are high imped-
ance when the Output Enable is at V
IH
.
Standby.
Standby disables most of the internal
circuitry allowing a substantial reduction of the cur-
rent consumption. The memory is in stand-by
when Chip Enable and Reset/Power-Down are at
V
IH
. The power consumption is reduced to the
stand-by level and the outputs are set to high im-
pedance, independently from the Output Enable
or Write Enable inputs. If Chip Enable switches to
V
IH
during a program or erase operation, the de-
vice enters Standby mode when finished.
Reset.
During Reset mode the memory is dese-
lected and the outputs are high impedance. The
memory is in Reset mode when Reset/Power-
Down is at V
IL
. The power consumption is reduced
to the Standby level, independently from the Chip
Enable, Output Enable or Write Enable inputs. If
Reset is pulled to V
SS
during a Program or Erase,
this operation is aborted and the memory content
is no longer valid.
Table 3. Bus Operations
Note: 1. X = Don’t care.
2. L can be tied to V
IH
if the valid address has been previously latched.
3. Depends on G.
Operation
E
G
W
L
RP
WAIT
DQ15-DQ0
Bus Read
V
IL
V
IL
V
IH
V
IL(2)
V
IH
Data Output
Bus Write
V
IL
V
IH
V
IL
V
IL(2)
V
IH
Hi-Z
Data Input
Address Latch
V
IL
X
V
IH
V
IL
V
IH
Data Output or Hi-Z
(3)
Output Disable
V
IL
V
IH
V
IH
X
V
IH
Hi-Z
Hi-Z
Standby
V
IH
X
X
X
V
IH
Hi-Z
Hi-Z
Reset
X
X
X
X
V
IL
Hi-Z
Hi-Z
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M58CR064D12ZB6T | 64 Mbit 4Mb x 16, Dual Bank, Burst 1.8V Supply Flash Memory |
| M58CR064P12ZB6T | 64 Mbit 4Mb x 16, Dual Bank, Burst 1.8V Supply Flash Memory |
| M58CR064Q12ZB6T | 64 Mbit 4Mb x 16, Dual Bank, Burst 1.8V Supply Flash Memory |
| M58CR064D85ZB6T | 64 Mbit 4Mb x 16, Dual Bank, Burst 1.8V Supply Flash Memory |
| M58CR064DZB | 64 Mbit 4Mb x 16, Dual Bank, Burst 1.8V Supply Flash Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M58CR064C85ZB6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit 4Mb x 16, Dual Bank, Burst 1.8V Supply Flash Memory |
| M58CR064C90ZB6T | 功能描述:閃存 64M (4Mx16) 90ns RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| M58CR064CZB | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit 4Mb x 16, Dual Bank, Burst 1.8V Supply Flash Memory |
| M58CR064D | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit 4Mb x 16, Dual Bank, Burst 1.8V Supply Flash Memory |
| M58CR064D10ZB6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit 4Mb x 16, Dual Bank, Burst 1.8V Supply Flash Memory |
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